ZiLOG Z8018 Series User Manual page 63

Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued)
Register
Timer Data Register Ch 0 L
Data Register Ch 0 H
Reload Register Ch 0 L
Reload Register Ch 0 H
Timer Control Register
Reserved
Data Register Ch 1 L
Data Register Ch 1 H
Reload Register Ch 1 L
Reload Register Ch 1 H
Others Free Running Counter
Reserved
Clock Multiplier Register
CPU Control Register
Family MPU User Manual
Mnemonic Binary
TMDR0L XX001100
TMDR0H XX001101
RLDR0L XX001110
RLDR0H XX001111
TCR XX010000
XX010001
TMDR1L XX010100
TMDR1H XX010101
RLDR1L XX010110
RLDR1H XX010111
FRC XX011000
XX011001
XX011111
CMR XX011110
CCR XX011111
Z8018x
Address
Hex Page
0CH 159
0DH 159
0EH 159
0FH 159
10H 161
11H
14H 160
15H 160
16H 160
17H 160
18H 172
19H
1DH
1EH 52
1FH 53
UM005004-0918
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