Table of Contents
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MNEMONICS
LD (DE),A
LD ww,mn
LD ww,(mn)
LDDR
LD (HL),m
LD HL,(mn)
LD (HL),g
LDI
LDI,A
LDIR
LD IX,mn
LID IX,(mn)
LD (IX+d),m
LD (IX+ d),g
LD IY,mn
LD IY,(mn)
LD (IY+d),m
LD (IY+d),g
LD (mn),A
LD (mn),ww
LD (mn),HL
LD (mn),IX
LD (mn),IY
LD R,A
LD g,(HL)
LD g,(IX+d)
LD g,(IY+d)
LD g,m
Family MPU User Manual
Machine
Bytes
Cycles
1
3
3
3
4
6
2
6
2
4
2
3
3
5
1
3
2
4
2
2
2
6
2
4
4
4
4
6
4
5
3
7
4
4
4
6
4
5
3
7
3
5
4
7
3
6
4
7
4
7
2
2
1
2
3
6
3
6
2
2
Z8018x
States
7
9
18
≠
14 (If BC
0)
R
12 (If BC
= 0
R
9
15
7
12
6
≠
14 (If BC
0)
R
12 (If BC
= 0)
R
12
18
15
15
12
18
15
15
13
19
16
19
19
6
6
14
14
6
UM005004-0918
241
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Do you have a question about the Z8018 Series and is the answer not in the manual?
Questions and answers
are there a timing diagrams for PUSH and POP instructions?
The timing diagrams for the PUSH and POP instructions for the ZiLOG Z8018 Series are as follows:
POP Instruction (e.g., POP IX or POP IY):
- Machine Cycle 1 (MC1): Fetch POP opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Read from memory at SP (Stack Pointer); data goes to low byte (e.g., IXL or IYL).
- Machine Cycle 4 (MC4): Read from memory at SP+1; data goes to high byte (e.g., IXH or IYH).
PUSH Instruction (e.g., PUSH IX or PUSH IY):
- Machine Cycle 1 (MC1): Fetch PUSH opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Decrement SP by 1 and write high byte (e.g., IXH or IYH) to memory at SP.
- Machine Cycle 4 (MC4): Decrement SP by 1 and write low byte (e.g., IXL or IYL) to memory at SP.
Each machine cycle includes three T-states (T1, T2, T3), and memory control signals (such as MREQ, RD, WR) are active as needed during these cycles.
This answer is automatically generated