ZiLOG Z8018 Series User Manual page 271

Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction Cycle
MC1
MC2
EX (SP),IX
EX (SP),IY
MC3
MC4
MC5
MC6
MC7
MC1
HALT
—
IM0 MC1
IM1
IM2
MC2
MC1
INC g
DEC g
MC2
MC1
INC (HL)
MC2
DEC (HL)
MC3
MC4
States Address Data
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
T1T2T3 SP DATA
T1T2T3 SP+1 DATA
Ti * Z
T1T2T3 SP+1 IXH
IYH
T1T2T3 SP IXL
IYL
T1T2T3 1st Op Code 1st Op
Address Code
— Next Op Code Next Op
Address Code
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
T1T2T3 1st Op Code 1st Op
Address Code
Ti * Z
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 HL DATA
Ti * Z
T1T2T3 HL DATA
Family MPU User Manual
RD WR MREQ IORQ M1 HALT ST
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
1 1 1 1
1 0 0 1
1 0 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
1 1 1 1
0 1 0 1
0 1 0 1
1 1 1 1
1 0 0 1
Z8018x
257
0 1 0
0 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
0 1 0
0 0 0
0 1 0
0 1 1
0 1 0
1 1 1
0 1 0
1 1 1
1 1 1
1 1 1
UM005004-0918