ZiLOG Z8018 Series User Manual page 282

Z8018x
Family MPU User Manual
268
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction Cycle
MC1
MC2
LDIR
LDDR
(If BCR≠0)
MC3
MC4
MC5~M
C6
MC1
LDIR
MC2
LDDR
(If BCR=0)
MC3
MC4
MC1
MC2
MLT ww**
MC3
~MC13
MC1
NEG
MC2
NOP MC1
UM005004-0918
States Address Data
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
T1T2T3 HL DATA
T1T2T3 DE DATA
TiTi * Z
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
T1T2T3 HL DATA
T1T2T3 DE DATA
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
TiTiTTi * Z
TiTiTiTi
TiTiTi
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
T1T2T3 1st Op Code 1st Op
Address Code
RD WR MREQ IORQ M1 HALT ST
0 1 0 1
0 1 0 1
0 1 0 1
1 0 0 1
1 1 1 1
0 1 0 1
0 1 0 1
0 1 0 1
1 0 0 1
0 1 0 1
0 1 0 1
1 1 1 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0
0 1 1
1 1 1
1 1 1
1 1 1
0 1 0
0 1 1
1 1 1
1 1 1
0 1 0
0 1 1
1 1 1
0 1 0
0 1 1
0 1 0