ZiLOG Z8018 Series User Manual page 267

Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction Cycle
AND (IY+ d) MC4
OR (IX + d) ~MC6
OR (IY+d)
XOR (IX + d)
XOR (IY+d)
CP (IX+d) MC6
CP (IY+d)
MC1
BIT b,g
MC2
MC1
BIT b, (HL)
MC2
MC3
MC1
MC2
BIT b, (IX+d)
BIT b, (IY+d)
MC3
MC4
MC5
States Address Data
TiTiTi * Z
T1T2T3 IX+d DATA
IY+d
T1T2T3 1st Op Code 1st
Address Op Code
T1T2T3 2nd Op Code 2nd
Address Op Code
T1T2T3 1st Op Code 1st
Address Op Code
T1T2T3 2nd Op Code 2nd
Address Op Code
T1T2T3 HL DATA
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
T1T2T3 1st operand d
Address
T1T2T3 3rd Op Code 3rd Op
Address Code
T1T2T3 IX+ d DATA
IY+d
Family MPU User Manual
RD WR MREQ IORQ M1 HALT ST
1 1 1 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
Z8018x
253
1 1 1
1 1 1
0 1 0
0 1 1
0 1 0
0 1 1
1 1 1
0 1 0
0 1 1
1 1 1
0 1 1
1 1 1
UM005004-0918