Figure 19. Memory And I/O Wait State Insertion (Dcntl - Dma/Wait Control Register); Table 3. Memory Wait States - ZiLOG Z8018 Series User Manual

Bit 7 6
MWI1 MWI0
R/W R/W
Figure 19. Memory and I/O Wait State Insertion (DCNTL – DMA/Wait
Control Register)
The number of Wait States (TW) inserted in a specific cycle is the
maximum of the number requested by the WAIT input, and the number
automatically generated by the on-chip Wait State generator.
Bit 7, 6: MWI1 MWI0, (Memory Wait Insertion)
For CPU and DMAC cycles which access memory (including memory
mapped I/O), zero to three Wait States may be automatically inserted
depending on the programmed value in MWI1 and MWI0 as depicted in
Table 3
Table 3. Memory Wait States
MW11 MWI0
0 0
0 1
1 0
1 1
Bit 5, 4: IWI1, IWI0 (I/O Wait Insertion)
For CPU and DMA cycles which access external I/O (and interrupt
acknowledge cycles), one to six Wait States (TW) may be automatically
5 4
MWI1 MWI0
R/W R/W
The Number of Wait States
0
1
2
3
Family MPU User Manual
UM005004-0918
Z8018x
29