Dynamic Ram Refresh Control; Figure 43. Int1, Int2 And Internal Interrupts Timing Diagram - ZiLOG Z8018 Series User Manual

Z8018x
Family MPU User Manual
86
Last MC
Phi
INT1,2
–
A0 A19
M1
MREQ
IORQ
RD
WR
–
D0 D7
ST
MC: Machine Cycle

Dynamic RAM Refresh Control

UM005004-0918
INT1, INT2, internal interrupt acknowledge cycle
T1 T2 TW* TW* T3 Ti T1
PC
Figure 43. INT1, INT2 and Internal Interrupts Timing Diagram
The Z8X180 incorporates a dynamic RAM refresh control circuit
including 8-bit refresh address generation and programmable refresh
timing. This circuit generates asynchronous refresh cycles inserted at the
programmable interval independent of CPU program execution. For
systems which do not use dynamic RAM, the refresh function can be
disabled.
When the internal refresh controller determines that a refresh cycle should
occur, the current instruction is interrupted at the first breakpoint between
machine cycles. The refresh cycle is inserted by placing the refresh
address on A0–A7 and the RFSH output is driven Low.
PC Stacking
T2 T3 T1 T2 T3 T1 T2
SP-2 Vector
SP-1
PCH PCL
* Two Wait States are automatically inserted.
Op Code
fetch cycle
Vector Table Read
T3 T1 T2 T3 T1 T2
Starting
Address
Vector+1
Starting Starting
address (L)
address (H)
T3