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Z8018x
Family MPU User Manual
228
Table 44.
Stock and Exchange (Continued)
Operation
Name
Mnemonics
Exchange EX AFAF'
EX DE, HL
EX X
EX (SP),HL
EX (SP),IX
EX (SP),IY
(4) In the case of POP AF, Flag is written as current contents of the stack
.
UM005004-0918
Addressing
Op Code
Immed Ext
Ind
00 001 000
11 101 011
11 011 001
11 100 011
11 011 101
11 111 101
11 100 011
Reg RegI Imp Rel
Bytes States
S/D
1
4
S/D
1
3
S/D
1
3
S/D
1
16
S/D
2
19
S/D
2
19
Flags
7 6 4 2
Operation
S Z H P/V N C
• • • •
AF
-AF
'
R
R
• • • •
DE
-HL
R
R
• • • •
BC
-BC
'
R
R
DE
→DE
'
R
R
→HL
HL
'
R
R
• • • •
Hr→(SP + 1)
M
Lr→(SP)
M
IXHr→(SP + 1)
• • • •
M
IXLr-(SP)
M
• • • •
IYHr-(SP + 1)
M
IYLr→(SP)
M
1 0
• •
• •
• •
• •
• •
• •
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Questions and answers
are there a timing diagrams for PUSH and POP instructions?
The timing diagrams for the PUSH and POP instructions for the ZiLOG Z8018 Series are as follows:
POP Instruction (e.g., POP IX or POP IY):
- Machine Cycle 1 (MC1): Fetch POP opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Read from memory at SP (Stack Pointer); data goes to low byte (e.g., IXL or IYL).
- Machine Cycle 4 (MC4): Read from memory at SP+1; data goes to high byte (e.g., IXH or IYH).
PUSH Instruction (e.g., PUSH IX or PUSH IY):
- Machine Cycle 1 (MC1): Fetch PUSH opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Decrement SP by 1 and write high byte (e.g., IXH or IYH) to memory at SP.
- Machine Cycle 4 (MC4): Decrement SP by 1 and write low byte (e.g., IXL or IYL) to memory at SP.
Each machine cycle includes three T-states (T1, T2, T3), and memory control signals (such as MREQ, RD, WR) are active as needed during these cycles.
This answer is automatically generated