ZiLOG Z8018 Series User Manual page 35

Wait States (TW) are inserted as previously described for Op Code fetch
cycles. Figure 11 illustrates the read/write timing without Wait States
(Tw), while Figure 12 illustrates read/write timing with Wait States (TW).
T1
Phi
–
A0 A19
–
D0 D7
WAIT
MREQ
RD
WR
Figure 11.
Read Cycle
T2 T3
Memory address
Read data
Memory Read/Write (without Wait State) Timing Diagram
Family MPU User Manual
Write Cycle
T1 T2
Memory address
Write data
Z8018x
T3 T1
UM005004-0918
21