Figure 42. Reti Instruction Sequence - ZiLOG Z8018 Series User Manual

Z8018x
Family MPU User Manual
84
–
A0 A18 (A19)
M1 (M1E = 1)
M1 (M1E = 0)
Note: RETI machine cycles 9 and 10 not shown.
UM005004-0918
Return from Subroutine (RETI) Instruction Sequence
When the / sequence is fetched by the Z8X180, it is recognized as
EDH 4DH
the RETI instruction sequence. The Z8X180 then refetches the RETI
instruction with four T-states in the
peripherals time to decode that cycle (See Figure 42). This procedure
allows the internal interrupt structure of the peripheral to properly decode
the instruction and behave accordingly.
The M1E bit of the Operation Mode Control Register (OMCR) must be
set to so that M1 signal is active only during the refetch of the RETI
0
instruction sequence. This condition is the desired operation when Z80
peripherals are connected to the Z8018X.
T1 T2 T3
Phi
PC
EDH
–
D0 D7
MREQ
RD
ST
Figure 42. RETI Instruction Sequence
The RETI instruction takes 22 T-states and 10 machine cycles. Table 10
lists the conditions of all the control signals during this sequence for the
cycle allowing the Z80
EDH
T1 T2 T3 Ti Ti Ti
PC + 1
4DH
T1 T2 T3 Ti T1 T2
PC
EDH
T3 T1
PC + 1
4DH