I/O Registers; Internal I/O Registers - ZiLOG Z8018 Series User Manual

I/O Registers

INTERNAL I/O REGISTERS

By programming IOA7 and IOA6 as the I/O control register, internal I/O
register addresses are relocatable within ranges from
the I/O address space.
Table 57.
Register
ASCI Control Register A
Channel 0:
ASCI Control Register A
Channel 1:
Internal I/O Registers
Mnemonics Address
CNTLA0 0 0
CNTLA1 0 1
Family MPU User Manual
Remarks
MPE
RE TE
bit
during RESET
0 0
0
R/W R/W R/W
R/W
Receive Enable
Multi Processor Enable
bit MPE RE TE
during RESET
0 0 0
R/W
R/W R/W R/W
Receive Enable
Multi Processor Enable
MOD 2 1 0
0 0 0 Start + 7 bit Data + 1 Stop
0 0 1 Start + 7 bit Data + 2 Stop
0 1 0 Start + 7 bit Data + Parity + 1 Stop
0 1 1 Start + 7 bit Data + Parity + 2 Stop
1 0 0 Start + 8 bit Data + 1 Stop
1 0 1 Start + 8 bit Data + 2 Stop
1 1 0 Start + 8 bit Data + Parity + 1 Stop
1 1 1 Start + 8 bit Data + Parity + 2 Stop
Z8018x
to
0000H 00FFH
MPBR/
RTS0 MOD2 MOD1 MOD0
EFR
1
0 0
invalid
R/W R/W R/W R/W R/W
MODE Selection
Multi Processor Bit Receive/
1
Error Flag Reset
Request to Send
Transmit Enable
MPBR/
CKA1D
MOD2 MOD1
MOD0
EFR
1 invalid 0 0
R/W R/W R/W R/W
MODE Selection
Multi Processor Bit Receive/
Error Flag Reset
CKA1 Disable
Transmit Enable
UM005004-0918
293
in
0
0
R/W