ZiLOG Z8018 Series User Manual page 151

Bit
Position Bit/Field
2 Break
Feature
Enable
1 Break
Detect
(RO)
0 Send
Break
Each ASCI channel control register B configures multiprocessor mode,
parity and baud rate selection.
ASCI0 Time Constant Low Register (I/O Address: 1AH) (Z8S180/L180-Class Processors
Only)
Bit 7
R/W R/W
Reset 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
ASCI0 Time Constant High Register (I/O Address: 1BH) (Z8S180/L180-Class Processors
Only)
Bit 7
R/W R/W
Reset 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
R/W Value Description
R/W 0 Break Feature Enable On
1 Break Feature Enable Off
R/W 0 Break Detect On
1 Break Detect Off
R/W 0 Normal Xmit
1 Drive TXA Low
6 5
R/W R/W
0 0
6 5
R/W R/W
0 0
Family MPU User Manual
4 3
R/W R/W R/W
0 0
4 3
R/W R/W R/W
0 0
Z8018x
2 1 0
R/W R/W
0 0 0
2 1 0
R/W R/W
0 0 0
UM005004-0918
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