ZiLOG Z8018 Series User Manual page 276

Z8018x
Family MPU User Manual
262
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction Cycle
MC1
MC2
LD g, (IX+d)
LD g, (IY+d)
MC3
MC4~M
C5
MC6
MC1
LD (HL),g
MC2
MC3
MC1
MC2
LD (IX + d),g
LD (IY + d),g
MC3
MC4~
MC6
MC7
MC1
LD (HL),m
MC2
MC3
UM005004-0918
States Address Data
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
T1T2T3 1st operand d
Address
TiTi * Z
T1T2T3 IX+d DATA
IY+d
T1T2T3 1st Op Code 1st Op
Address Code
Ti * Z
T1T2T3 HL g
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
T1T2T3 1st operand d
Address
TiTiTi * Z
T1T2T3 IX+d g
IY+d
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 1st operand m
Address
T1T2T3 HL DATA
RD WR MREQ IORQ M1 HALT ST
0 1 0 1
0 1 0 1
0 1 0 1
1 1 1 1
0 1 0 1
0 1 0 1
1 1 1 1
1 0 0 1
0 1 0 1
0 1 0 1
0 1 0 1
1 1 1 1
1 0 0 1
0 1 0 1
0 1 0 1
1 0 0 1
0 1 0
0 1 1
1 1 1
1 1 1
1 1 1
0 1 0
1 1 1
1 1 1
0 1 0
0 1 1
1 1 1
1 1 1
1 1 1
0 1 0
1 1 1
1 1 1