ZiLOG Z8018 Series User Manual page 76

Z8018x
Family MPU User Manual
62
MMU Bank Base Register (BBR: 39H)
Bit
Bit/Field BB7
R/W R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field
– –
7 0 BB7
UM005004-0918
MMU Bank Base Register (BBR)
BBR specifies the base address (on 4KB boundaries) used to generate a
20-bit physical address for Bank Area accesses. All bits of BBR are reset
to during RESET.
0
7 6
BB6 BB5
R/W R/W
0 0
R/W Value Description
0 R/W
Physical Address Translation
Figure 29 illustrates the way in which physical addresses are generated
based on the contents of CBAR, CBR and BBR. MMU comparators
classify an access by logical area as defined by CBAR. Depending on
which of the three potential logical areas (Common Area 1, Bank Area, or
Common Area 0) is being accessed, the appropriate 8- or 7-bit base
address is added to the high-order 4 bits of the logical address, yielding a
19- or 20-bit physical address. CBR is associated with Common Area 1
accesses. Common Area 0, if defined, is always based at physical address
.
00000H
5 4
BB4 BB3
R/W R/W
0 0
BBR specifies the base address (on 4KB boundaries) used
to generate a 20-bit physical address for Bank Area
accesses.
3 2
BB2 BB1
R/W R/W
0 0
1 0
BB0
R/W
0 0