Sign In
Upload
Download
Table of Contents
Contents
Add to my manuals
Delete from my manuals
Share
URL of this page:
HTML Link:
Bookmark this page
Add
Manual will be automatically added to "My Manuals"
Print this page
×
Bookmark added
×
Added to my manuals
Manuals
Brands
ZiLOG Manuals
Computer Hardware
Z80180
User manual
ZiLOG Z80180 User Manual
Mpu
Hide thumbs
1
2
3
4
Table Of Contents
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
page
of
317
Go
/
317
Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
Z80180, Z8S180, Z8L180 MPU Operation
Features
General Description
Figure 1. 64-Pin DIP
Figure 2. 68-Pin PLCC
Figure 3. 80-Pin QFP
Figure 4. Z80180/Z8S180/Z8L180 Block Diagram
Pin Description
Table 1. Status Summary
Architecture
Table 2. Multiplexed Pin Descriptions
Operation Modes
Figure 5. Operation Mode Control Register
Figure 6. M1 Temporary Enable Timing
Figure 7. I/O Read and Write Cycles with IOC
Figure 8. I/O Read and Write Cycles with IOC
CPU Timing
Figure 9. Op Code Fetch (Without Wait State) Timing Diagram
Figure 10. Op Code Fetch (with Wait State) Timing Diagram
Figure 13. I/O Read/Write Timing Diagram
Figure 14. Instruction Timing Diagram
Figure 15. RESET Timing Diagram
Figure 16. Bus Exchange Timing During Memory Read
Wait State Generator
Figure 17. Bus Exchange Timing During CPU Internal Operation
Figure 18. WAIT Timing Diagram
Figure 19. Memory and I/O Wait State Insertion (DCNTL - Dma/Wait Control Register)
Table 3. Memory Wait States
Table 4. Wait State Insertion
HALT and Low Power Operation Modes (Z80180-Class Processors Only)
Figure 20. HALT Timing Diagram
Figure 21. SLEEP Timing Diagram
Low Power Modes (Z8S180/Z8L180 Only)
Add-On Features
STANDBY Mode
Table 5. Power-Down Modes (Z8S180/Z8L180-Class Processor Only)
STANDBY Mode Exit Wiht BUS REQUEST
STANDBY Mode Exit with External Interrupts
IDLE Mode
STANDBY-QUICK RECOVERY Mode
Internal I/O Registers
Figure 22. I/O Address Relocation
Table 6. I/O Address Map for Z80180-Class Processors Only
Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only)
Figure 23. Logical Address Mapping Examples
Figure 24. Physical Address Transition
Figure 25. MMU Block Diagram
Figure 26. I/O Address Translation
Figure 27. Logical Memory Organization
Figure 28. Logical Space Configuration
MMU Register Description
Figure 29. Physical Address Generation
Figure 30. Physical Address Generation 2
Interrupts
Figure 31. Interrupt Sources
Table 8. State of IEF1 and IEF2
Figure 32. TRAP Timing Diagram -2Nd Op Code Undefined
Figure 33. TRAP Timing - 3Rd Op Code Undefined
Figure 34. NMI Use
Figure 35. NMI Timing
Figure 36. INT0 Mode 0 Timing Diagram
Figure 37. INT0 Mode 1 Interrupt Sequence
Figure 38. INT0 Mode 1 Timing
Figure 39. INT0 Mode 2 Vector Acquisition
Figure 40. INT0 Interrupt Mode 2 Timing Diagram
Figure 41. INT1, INT2 Vector Acquisition
Interrupt Acknowledge Cycle Timings
Table 9. Vector Table
Interrupt Sources During RESET
Figure 42. RETI Instruction Sequence
Table 10. RETI Control Signal States
Dynamic RAM Refresh Control
Figure 43. INT1, INT2 and Internal Interrupts Timing Diagram
Figure 44. Refresh Cycle Timing Diagram
Table 11. DRAM Refresh Intervals
DMA Controller (DMAC)
Figure 45. DMAC Block Diagram
Table 12. Channel 0 Destination
Table 13. Channel 0 Source
Table 14. Transfer Mode Combinations
Table 15. Channel 1 Transfer Mode
Figure 46. DMA Timing Diagram-CYCLE STEAL Mode
Figure 47. CPU Operation and DMA Operation DREQ0 Is Programmed for Level-Sense
Figure 48. CPU Operation and DMA Operation DREQ0 Is Programmed for Edge-Sense
Figure 49. TEND0 Output Timing Diagram
Table 16. DMA Transfer Request
Figure 50. DMA Interrupt Request Generation
Asynchronous Serial Communication Interface (ASCI)
Figure 51. NMI and DMA Operation Timing Diagram
Figure 52. ASCI Block Diagram
Table 17. Data Formats
Table 18. Divide Ratio
Figure 53. DCD0 Timing Diagram
Figure 54. RTS0 Timing Diagram
Figure 55. ASCI Interrupt Request Circuit Diagram
Figure 56. ASCI Clock
Table 19. ASCI Baud Rate Selection
Baud Rate Generator
(Z8S180/Z8L180-Class Processors Only)
Table 20. Clock Mode Bit Values
Table 21. 2^Ss Values
Clocked Serial I/O Port (CSI/O)
CSI/O Registers Description
Figure 57. CSI/O Block Diagram
Table 22. CSI/O Baud Rate Selection
Figure 58. CSI/O Interrupt Request Generation
Figure 59. Transmit Timing Diagram-Internal Clock
Figure 60. Transmit Timing-External Clock
Figure 61. CSI/O Receive Timing-Internal Clock
Programmable Reload Timer (PRT)
Figure 62. CSI/O Receive Timing-External Clock
Figure 63. PRT Block Diagram
Table 23. Timer Output Control
Figure 65. Timer Output Timing Diagram
Figure 66. PRT Interrupt Request Generation
Table 24. E Clock Timing in each Condition
Figure 67. E Clock Timing Diagram
Figure 68. E Clock Timing in BUS RELEASE Mode
Figure 69. E Clock Timing in SLEEP Mode and
Figure 70. External Clock Interface
Table 25. Z8X180 Operating Frequencies
Figure 71. Clock Generator Circuit
Figure 72. Circuit Board Design Rules
Figure 73. Example of Board Design
Miscellaneous
Software Architecture
Instruction Set
Table 26. Instruction Set Summary
CPU Registers
Figure 74. CPU Register Configurations
Figure 75. Register Direct - Bit Field Definitions
Figure 76. Register Indirect Addressing
Figure 77. Indexed Addressing
Figure 78. Extended Addressing
Figure 79. Immediate Addressing
Figure 80. Relative Addressing
DC Characteristics
Absolute Maximum Rating
Table 27. Absolute Maximum Rating
Z80180 DC Characteristics
Table 28. Z80180 DC Characteristics
Z8S180 DC Characteristics
Table 29. Z8S180 DC Characteristics
Z8L180 DC Characteristics
Table 30. Z8L180 DC Characteristics
AC Characteristics
AC Characteristics-Z8S180
Table 31. Z8S180 AC Characteristics
Timing Diagrams
Figure 81. AC Timing Diagram 1
Figure 82. AC Timing Diagram 2
Figure 84. DMA Control Signals
Figure 85. E Clock Timing (Memory R/W Cycle) (I/O R/W Cycle)
Figure 87. E Clock Timing
Figure 88. Timer Output Timing
Figure 89. SLP Execution Cycle Timing Diagram
Figure 90. CSI/O Receive/Transmit Timing Diagram
Figure 91. External Clock Rise Time and Fall Time
Figure 92. Input Rise Time and Fall Time
Standard Test Conditions
Figure 93. Test Setup
Instruction Set
Register
Bit
Table 32. Register Values
Condition
Table 33. Bit Values
Table 34. Instruction Values
Restart Address
Flag
Table 35. Address Values
Table 36. Flag Conditions
Miscellaneous
Table 37. Operations Mnemonics
Data Manipulation Instructions
Table 38. Arithmetic and Logical Instructions (8-Bit)
Table 39. Rotate and Shift Instructions
Table 40. Arithmetic Instructions (16-Bit)
Data Transfer Instructions
Table 41. 8-Bit Load
Table 42. 16-Bit Load
Table 43. Block Transfer
Table 44. Stock and Exchange
Program and Control Instructions
Table 45. Program Control Instructions
Table 46. I/O Instructions
Special Control Instructions
Table 47. Special Control Instructions
Instruction Summary
Op Code Map
Table 48. 1St Op Code Map Instruction Format: XX
Table 49. 2Nd Op Code Map Instruction Format: CB XX
Table 50. 2Nd Op Code Map Instruction Format: ED XX
Bus Control Signal Conditions
Bus and Control Signal Condition in each Machine Cycle
Table 51. Bus and Control Signal Condition in each Machine Cycle
Interrupts
Table 52. Interrupts
Operating Modes Summary
Request Acceptances in each Operating Mode
Request Priority
Table 53. Request Acceptances in each Operating Mode
Table 54. the Z80180 Types of Requests
Operation Mode Transition
Other Operation Mode Transitions
Status Signals
Pin Outputs in each Operating Mode
Table 55. Pin Outputs in each Operating Mode
Pin Status
Table 56. Pin Status During RESET and LOW POWER OPERATION Modes
I/O Registers
Internal I/O Registers
Table 57. Internal I/O Registers
Ordering Information
Advertisement
Quick Links
Download this manual
Z8018x
Family MPU
User Manual
UM005004-0918
www.zilog.com
Table of
Contents
Previous
Page
Next
Page
1
2
3
4
5
Advertisement
Table of Contents
Need help?
Do you have a question about the Z80180 and is the answer not in the manual?
Ask a question
Questions and answers
Related Manuals for ZiLOG Z80180
Computer Hardware ZiLOG Z8 Encore! Z8F04A08100KIT User Manual
Z8 encore! xp 4k series 8-pin development kit (24 pages)
Computer Hardware ZiLOG Z80 Handbook
(297 pages)
Computer Hardware ZiLOG Z80 Reference Card
(16 pages)
Computer Hardware ZiLOG Z8018 Series User Manual
Mpu (317 pages)
Computer Hardware ZiLOG Z8S180 User Manual
Mpu (317 pages)
Computer Hardware ZiLOG Z80182 User Manual
Mpu (317 pages)
Computer Hardware ZiLOG Z86C5000ZEM Quick Start Manual
Icebox z8 family in-circuit emulator –c50 (4 pages)
Computer Hardware ZiLOG Z80-AIO Hardware User Manual
(48 pages)
Computer Hardware ZiLOG Z80-CPU Technical Manual
(83 pages)
Computer Hardware ZiLOG Z80A-CPU Technical Manual
(83 pages)
Computer Hardware ZiLOG Z8 GP ZGP323 User Manual
Programming system with usb interface (11 pages)
Computer Hardware Zilog System 8000 Hardware Reference Manual
(366 pages)
Computer Hardware ZiLOG eZ80F91 User Manual
Development kit (87 pages)
Computer Hardware ZiLOG eZ80 User Manual
(411 pages)
Computer Hardware ZiLOG eZ80 User Manual
Sales demonstration platform (21 pages)
Computer Hardware ZiLOG eZ8 User Manual
(240 pages)
Table of Contents
Print
Rename the bookmark
Delete bookmark?
Delete from my manuals?
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL
Need help?
Do you have a question about the Z80180 and is the answer not in the manual?
Questions and answers