Figure 14. Instruction Timing Diagram - ZiLOG Z8018 Series User Manual

Z8018x
Family MPU User Manual
24
T1 T2 T3 T1
Phi
–
A0 A19
–
D0 D7
M1
MREQ
RD
WR
Machine Cycle
NOTE: d = displacement
g = register contents
UM005004-0918
1st Op Code 2nd Op Code
Fetch Cycle Fetch Cycle
T2 T3 T1
PC PC+1
–
(DDH) (7OH
MC1 MC2
Figure 14. Instruction Timing Diagram
This instruction moves the contents of a CPU register (g) to the memory
location with address computed by adding a signed 8-bit displacement (d)
to the contents of an index register (IX).
The instruction cycle begins with the two machine cycles to read the two
byte instruction Op Code as indicated by M1 Low. Next, the instruction
operand (d) is fetched.
CPU internal
Displacement
Operation
Read Cycle
T2 T3 T1 T1 T1 T1
PC+2
d
77H)
MC3 MC4 MC5 MC6
Next instruction
Memory
Fetch Cycle
Write Cycle
T2 T3 T1 T2
PC+3
IX+d
g
MC7