ZiLOG Z8018 Series User Manual page 68

Z8018x
Family MPU User Manual
54
Bit
Position Bit/Field
2 LNIO
1 LNCPUCTL
0 LNAD/
DATA
UM005004-0918
R/W Value Description
R/W 0
1
R/W 0
1
R/W 0
1
Memory Management Unit (MMU)
The Z8X180 features an on-chip MMU which performs the translation of
the CPU 64KB (16-bit addresses
address space into a 1024KB (20-bit addresses
physical memory address space. Address translation occurs internally in
parallel with other CPU operation.
Logical Address Spaces
The 64KB CPU logical address space is interpreted by the MMU as
consisting of up to three separate logical address areas, Common Area 0,
Bank Area, and Common Area 1.
As depicted in Figure 23, a variety of logical memory configurations are
possible. The boundaries between the Common and Bank Areas can be
programmed with 4KB resolution.
Standard Drive
33% Drive on certain external I/O
Standard Drive
33% Drive on CPU control signals
Standard Drive
33% drive on A10–A0, D7–D0
to
0000H
) logical memory
FFFFH
to
00000H FFFFFH
)