ZiLOG Z8018 Series User Manual page 77

Z8018x
Family MPU User Manual
63
MMU and RESET
During RESET, all bits of the CA field of CBAR are set to while all bits
1
of the BA field of CBAR, CBR and BBR are reset to . The logical 64KB
0
address space corresponds directly with the first 64KB to )
0000H FFFFH
of the 1024KB . to ) physical address space. Thus, after
00000H FFFFFH
RESET, the Z8X180 begins execution at logical and physical address 0.
MMU Register Access Timing
When data is written into CBAR, CBR or BBR, the value is effective
from the cycle immediately following the I/O write cycle which updates
these registers.
During MMU programming insure that CPU program execution is not
disrupted. The next cycle following MMU register programming is
normally an Op Code fetch from the newly translated address. One
technique is to localize all MMU programming routines in a Common
Area that is always enabled.
UM005004-0918