Figure 67. E Clock Timing Diagram; Figure 68. E Clock Timing In Bus Release Mode - ZiLOG Z8018 Series User Manual

Op Code Memory Read/
Fetch Cycle
T1 T2 T3
Phi
E
M1
MREQ
IORQ
NOTE : MC = Machine Cycle
Figure 67.
Last
state
Phi
BUSREQ
BUSACK
E
Figure 68.
Write Cycle
I/O Read Cycle
T1 T2 T3 T1 T2 Tw T3
E Clock Timing Diagram (During Read/Write Cycle and
Interrupt Acknowledge Cycle
BUS RELEASE mode
TX TX
E
E
E Clock Timing in BUS RELEASE Mode
Family MPU User Manual
NMI
Acknowledge
I/O Write Cycle
1st MC
T1 T2 T3 T1 T2 T3
* Two wait states are automatically inserted
TX TX
E
Z8018x
INT0 Acknowledge
1st MC
T1 T2 Tw* Tw* T3
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