Operating Modes Summary; Request Acceptances In Each Operating Mode - ZiLOG Z8018 Series User Manual

Operating Modes Summary

REQUEST ACCEPTANCES IN EACH OPERATING MODE

Table 53.
Current Normal
Status Operation
(CPU mode
and IOSTOP
Request Mode)
WAIT Acceptable
Refresh Request Refresh cycle
Request of Refresh begins at the
by the on-chip end of Machine
Refresh Controller Cycle (MC)
DREQ0 DMA cycle
DREQ1 begins at the
end of MC
BUSREQ Bus is released
at the end of
MC
Interrupt INT0, Accepted after
INT1, executing the
1NT2 current
instruction.
Request Acceptances in Each Operating Mode
Interrupt
Refresh Acknowledge
WAIT State Cycle Cycle
Acceptable Not Acceptable
acceptable
Not Not Refresh cycle
acceptable acceptable begins at the
end MC
DMA cycle Acceptable Acceptable
begins at the Refresh cycle DMA cycle
end of MC precedes. begins at the
DMA cycle end of MC.
begins at the
end of one
MC
Not Not Bus is released
acceptable acceptable at the end of
MC
Accepted Not Not
after acceptable acceptable
executing the
current
instruction
Family MPU User Manual
BUS
RELEASE SLEEP
DMA Cycle Mode Mode
Acceptable Not Not
acceptable acceptable
Refresh cycle Not Not
begins at the acceptable acceptable
end of MC
Acceptable Acceptable Not
Refer to *After BUS acceptable
"DMA RELEASE
Controller" cycle, DMA
for details. cycle begins
at the end of
one MC
Bus is Continue Acceptable
released at the BUS
end of MC RELEASE
mode
Not Not Acceptable
acceptable acceptable Return from
SLEEP
mode to
normal
operation.
UM005004-0918
Z8018x
281
SYSTEM
STOP
Mode
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable
Acceptable
Return from
SYSTEM
STOP mode
to normal
operation