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Z8018x
Family MPU User Manual
2
on-chip memory management unit (MMU) with the capability of
addressing up to 1 MB of memory.
Reduced system costs are obtained by incorporating several key system
functions on-chip with the CPU. These key functions include I/O devices
such as DMA, UART, and timer channels. Also included on-chip are
several glue functions such as dynamic RAM refresh control, wait state
generators, clock oscillator, and interrupt controller.
Not only does the Z8X180 consume a low amount of power during
normal operation, but processors with Z8S180 and Z8L180 class
processors also provides two operating modes that are designed to
drastically reduce the power consumption even further. The SLEEP mode
reduces power by placing the CPU into a stopped state, thereby
consuming less current, while the on-chip I/O device is still operating.
The SYSTEM STOP mode places both the CPU and the on-chip
peripherals into a stopped state, thereby reducing power consumption
even further.
When combined with other CMOS VLSI devices and memories, the
Z8X180 provides an excellent solution to system applications requiring
high performance, and low power operation.
Figures 1 through 3 illustrate the three pin packages in the Z8X180 MPU
family:
•
•
•
Pin out package descriptions for other Z8X180-based products are
covered in their respective product specifications.
Figure 4 depicts the block diagram that is shared throughout all
configurations of the Z8X180.
UM005004-0918
64-Pin Dual In-line Package (DIP), Figure 1
68-Pin Plastic Leaded Chip Carrier (PLCC), Figure 2
80-Pin Quad Flat Pack (QFP), Figure 3
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Do you have a question about the Z8018 Series and is the answer not in the manual?
Questions and answers
are there a timing diagrams for PUSH and POP instructions?
The timing diagrams for the PUSH and POP instructions for the ZiLOG Z8018 Series are as follows:
POP Instruction (e.g., POP IX or POP IY):
- Machine Cycle 1 (MC1): Fetch POP opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Read from memory at SP (Stack Pointer); data goes to low byte (e.g., IXL or IYL).
- Machine Cycle 4 (MC4): Read from memory at SP+1; data goes to high byte (e.g., IXH or IYH).
PUSH Instruction (e.g., PUSH IX or PUSH IY):
- Machine Cycle 1 (MC1): Fetch PUSH opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Decrement SP by 1 and write high byte (e.g., IXH or IYH) to memory at SP.
- Machine Cycle 4 (MC4): Decrement SP by 1 and write low byte (e.g., IXL or IYL) to memory at SP.
Each machine cycle includes three T-states (T1, T2, T3), and memory control signals (such as MREQ, RD, WR) are active as needed during these cycles.
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