Figure 21. Sleep Timing Diagram - ZiLOG Z8018 Series User Manual

SLP 2nd Op Code
Fetch Cycle
T2 T3
Phi
INT1, NMI
–
A0 A19
SLP 2nd Op Code address
HALT
M1
Figure 21. SLEEP Timing Diagram
IOSTOP Mode
IOSTOP mode is entered by setting the IOSTOP bit of the I/O Control
Register (ICR) to
operating. However, the CPU continues to operate. Recovery from
IOSTOP mode is by resetting the IOSTOP bit in ICR to
SYSTEM STOP Mode
SYSTEM STOP mode is the combination of SLEEP and IOSTOP modes.
SYSTEM STOP mode is entered by setting the IOSTOP bit in ICR to
followed by execution of the SLP instruction. In this mode, on-chip I/O
and CPU stop operating, reducing power consumption. Recovery from
SYSTEM STOP mode is the same as recovery from SLEEP mode, noting
that internal I/O sources, (disabled by IOSTOP) cannot generate a
recovery interrupt.
SLEEP mode
T1 T2 TS
FFFFFH
. In this case, on-chip I/O (ASCI, CSI/O, PRT) stops
1
Family MPU User Manual
Op Code Fetch or Interrupt
Acknowledge Cycle
TS T1 T2
.
0
UM005004-0918
Z8018x
35
T3
1