Figure 48. Cpu Operation And Dma Operation Dreq0 Is Programmed For Edge-Sense; Figure 49. Tend0 Output Timing Diagram - ZiLOG Z8018 Series User Manual

Z8018x
Family MPU User Manual
108
Phi
DREQ0
Phi
TEND0
UM005004-0918
rising edge of the clock prior to T3 at which time the DMA operation
(re)starts. Figure 48 depicts the edge-sense DMA timing.
DMA CPU
Write Machine
Cycle Cycle
Tw T3 T1 T2 T3
**
**
Figure 48. CPU Operation and DMA Operation DREQ0 is Programmed
for Edge-Sense
During the transfers for channel 0, the TEND0 output goes Low
synchronous with the write cycle of the last (BCR0 =
(Reference Figure 49).
Last DMA cycle (BCR0 = 00H)
DMA read cycle
T1 T2
Figure 49. TEND0 Output Timing Diagram
The DREQ0 and TEND0 pins are programmably multiplexed with the
CKA0 and CKA1 ASCI clock input/outputs. However, when DMA
channel 0 is programmed for memory to/from I/O (and memory to/from
DMA DMA
Read Write
Cycle Cycle
T1 T2 T3 T1 T2 Tw
**
DMA write cycle
T3 T1 T2
CPU
Machine
Cycle
T3 T1 T2 T3
**
** DREQ0 is sampled at
) DMA transfer
OOH
TW T3