ZiLOG Z8018 Series User Manual page 143

Bit
Position Bit/Field R/W
5 TE
4 CKA1D
3 MPBR/
EFR
Value Description
R/W Transmitter Enable — When TE is set to 1, the ASCI
transmitter is enabled. When TE is reset to 0, the
transmitter is disabled and any transmit operation in
progress is interrupted. However, the TDRE flag is not
reset and the previous contents of TDRE are held. TE is
cleared to 0 in IOSTOP mode, and during RESET.
R/W CKA1 Clock Disable — When CKA1D is set to 1, the
multiplexed CKA1/
function. When CKA1 D is 0, the pin is used as CKA1, an
external data dock input/output for channel 1
R/W Multiprocessor Bit Receive/Error Flag Reset — When
multiprocessor mode is enabled (MP in CNTLB is 1),
MPBR, when read, contains the value of the MPB bit for
the last receive operation. When written to 0, the EFR
function is selected to reset all error flags (OVRN, FE and
PE) to 0. MPBR/EFR is undefined during RESET.
Family MPU User Manual
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pin is used for the
UM005004-0918
Z8018x
129
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