Figure 47. Cpu Operation And Dma Operation Dreq0 Is Programmed For Level-Sense - ZiLOG Z8018 Series User Manual

Memory to I/O (Memory Mapped I/O) — Channel 0
For memory to/from I/O (and memory to/from memory mapped I/O) the
DREQ0 input is used to time the DMA transfers. In addition, the TEND0
(Transfer End) output is used to indicate the last (byte count register
BCR0 =
00H
The DREQ0 input can be programmed as level- or edge-sensitive.
When level-sense is programmed, the DMA operation begins when
DREQ0 is sampled Low. If DREQ0 is sampled High, after the next DMA
byte transfer, control is relinquished to the Z8X180 CPU. As illustrated in
Figure 47, DREQ0 is sampled at the rising edge of the clock cycle prior to
T3, (that is, either T2 or Tw).
DMA
Write
Cycle
Tw Tw T3
Phi
**
DREQ0
Figure 47.
When edge-sense is programmed, DMA operation begins at the falling
edge of DREQ0 If another falling edge is detected before the rising edge
of the clock prior to T3 during DMA write cycle (that is T2 or Tw), the
DMAC continues operating. If an edge is not detected, the CPU is given
control after the current byte DMA transfer completes. The CPU
continues operating until a DREQ0 falling edge is detected before the
) transfer.
DMA
CPU
Read
Machine
Cycle
Cycle
T1 T2 T3 T1 T2 T3
**
CPU Operation and DMA Operation DREQ0 is Programmed
for Level-Sense
Family MPU User Manual
DMA
Write
Cycle (I/O)
T1 T2 Tw Tw T3 T1
**
** DREQ0 is sampled at
Z8018x
107
T2
UM005004-0918