Table 39. Rotate And Shift Instructions - ZiLOG Z8018 Series User Manual

Mpu
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Table 39.
Rotate and Shift Instructions (Continued)
Operation
Name
Mnemonics
Op Code
RLC (IX + d)
11 011 101
11 001 011
<d>
00 000 110
RLC (IY + d)
11 111 101
11 001 011
<d>
00 000 110
RLD
11 101 101
01 101 111
RRA
00 011 111
RRg
11 001 011
00 011 g
RR (HL)
11 001 011
00 011 110
RR (IX + d)
11 011 101
11 001 011
<d>
00 011 110
RR (IY + d)
11 111 101
11 001 011
<d>
00 011 110
RRCA
00 001 111
RRC g
11 001 011
00 001 g
RRC (HL)
11 001 011
00 001 110
RRC (IX + d)
11 011 101
11 001 011
<d>
00 001 110
RRC (IY + d)
11 111 101
Addressing
Immed Ext Ind Reg Regi Imp Rel
S/D
S/D
S/D
S/D
S/D
S/D
S/D
S/D
S/D
S/D
S/D
S/D
S/D
Family MPU User Manual
State
Bytes
s
Operation
4
19
4
19
2
16
C
b7
1
3
2
7
2
13
4
19
b0
4
19
1
3
2
7
2
13
4
19
4
19
Z8018x
217
Flags
7 6 4 2
1 0
S Z H P/V N C
↑ ↑ R P
R ↑
↑ ↑ R P
R ↑
↑ ↑ R P
R •
b0
• • R •
R ↑
↑ ↑ R P
R ↑
↑ ↑ R P
R ↑
↑ ↑ R P
R ↑
b7
C
↑ ↑ R P
R ↑
• • R •
R ↑
↑ ↑ R P
R ↑
↑ ↑ R P
R ↑
↑ ↑ R P
R ↑
↑ ↑ R P
R ↑
UM005004-0918

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Questions and answers

Sam Sawyer
January 25, 2025

are there a timing diagrams for PUSH and POP instructions?

1 comments:
Mr. Anderson
May 14, 2025

The timing diagrams for the PUSH and POP instructions for the ZiLOG Z8018 Series are as follows:

POP Instruction (e.g., POP IX or POP IY):
- Machine Cycle 1 (MC1): Fetch POP opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Read from memory at SP (Stack Pointer); data goes to low byte (e.g., IXL or IYL).
- Machine Cycle 4 (MC4): Read from memory at SP+1; data goes to high byte (e.g., IXH or IYH).

PUSH Instruction (e.g., PUSH IX or PUSH IY):
- Machine Cycle 1 (MC1): Fetch PUSH opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Decrement SP by 1 and write high byte (e.g., IXH or IYH) to memory at SP.
- Machine Cycle 4 (MC4): Decrement SP by 1 and write low byte (e.g., IXL or IYL) to memory at SP.

Each machine cycle includes three T-states (T1, T2, T3), and memory control signals (such as MREQ, RD, WR) are active as needed during these cycles.

This answer is automatically generated

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