ZiLOG Z8018 Series User Manual page 256

Z8018x
Family MPU User Manual
242
UM005004-0918
MNEMONICS
LD g,g'
LD SP,HL
LD SP,IX
LD SP,IY
MLT ww"
NEG
NOP
OR (HL)
OR (IX+d)
OR (IY+d)
OR m
OR g
OTDM**
OTDMR**
OTDR
OTIM**
OTIMR**
OTIR
OUTD
OUTI
OUT (m),A
OUT (C),g
OUT0 (m),g **
POP IX
POP IY
POP zz
Machine
Bytes Cycles
1 2
1 2
2 3
2 3
2 13
2 2
1 1
1 2
3 6
3 6
2 2
1 2
2 6
2 8
2 6
2 6
2 4
2 6
2 8
2 6
2 6
2 4
2 4
2 4
2 4
2 4
3 5
2 4
2 4
1 3
States
4
4
7
7
17
6
3
6
14
14
6
4
14
≠
16 (If Br 0)
14 (If Br = 0)
≠
14 (If Br 0)
12 (If Br = 0
14
≠
16 (If Br 0)
14 (If Br = 0)
≠
14 (If Br 0)
12 (If Br = 0)
12
12
10
10
13
12
12
9