Figure 33. Trap Timing - 3Rd Op Code Undefined - ZiLOG Z8018 Series User Manual

Z8018x
Family MPU User Manual
72
3rd Op Code
Fetch Cycle
T1 T2 T3
Phi
–
A0 A19
–
D0 D7
MI
MREQ
RD
WR
UM005004-0918
Memory
Read Cycle
T1 T2 TTP T3
PC
IX+d, IY+d
Undefined
Op Code
Figure 33. TRAP Timing - 3rd Op Code Undefined
External Interrupts
The Z8X180 features four external hardware interrupt inputs:
•
NMI–Non-maskable interrupt
•
INT0–Maskable Interrupt Level 0
•
INT1–Maskable Interrupt Level 1
•
INT2–Maskable Interrupt Level 2
NMI, INT1, and INT2 feature fixed interrupt response modes. INT0 has 3
different software programmable interrupt response modes—Mode 0,
Mode 1 and Mode 2.
NMI - Non-Maskable Interrupt
The interrupt input is edge-sensitive and cannot be masked by
NMI
software. When
NMI
T1 Ti Ti Ti T1 T2
SP-1
PCH
is detected, the Z8X180 operates as follows:
Restart from 0000H
PC stacking
Op Code
fetch cycle
T3 T1 T2 T3 T1 T2 T3
SP-2
0000H
PCL