Figure 7. I/O Read And Write Cycles With Ioc; Figure 8. I/O Read And Write Cycles With Ioc - ZiLOG Z8018 Series User Manual

T1
Phi
IORQ
RD
WR
Figure 7. I/O Read and Write Cycles with IOC = 1 Timing Diagram
When IOC is
0
required by the Z80 family of peripherals. The IORQ and RD signals go
active as a result of the rising edge of T2. This timing allows the Z8X180
to satisfy the setup times required by the Z80 peripherals on those two
signals (Figure ).
T1
Phi
IORQ
RD
WR
Figure 8. I/O Read and Write cycles with IOC = 0 Timing Diagram
For the remainder of this document, assume that M1E is
T2
TW
, the timing of the IORQ and RD signals match the timing
T2
TW
Family MPU User Manual
T3
T3
and IOC is
0
UM005004-0918
Z8018x
17
.
0