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Z8018x
Family MPU User Manual
140
RTS0 Flag
RTS0 Pin
DCD0
RDRF0
OVRN0
PE0
FE0
RDRF1
OVRN1
PE1
FE1
UM005004-0918
I/O Instruction
Phi
WR
Figure 54.
RTS0 Timing Diagram
Figure 55 illustrates the ASCI interrupt request generation circuit.
RIE0
TDRE0
TIE0
RIE1
TDRE1
TIE1
Figure 55.
ASCI Interrupt Request Circuit Diagram
I/O write cycle
T2
T1
IEF1
T3
T1
ASCI0 Interrupt
Request
ASCI1 Interrupt
Request
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Questions and answers
are there a timing diagrams for PUSH and POP instructions?
The timing diagrams for the PUSH and POP instructions for the ZiLOG Z8018 Series are as follows:
POP Instruction (e.g., POP IX or POP IY):
- Machine Cycle 1 (MC1): Fetch POP opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Read from memory at SP (Stack Pointer); data goes to low byte (e.g., IXL or IYL).
- Machine Cycle 4 (MC4): Read from memory at SP+1; data goes to high byte (e.g., IXH or IYH).
PUSH Instruction (e.g., PUSH IX or PUSH IY):
- Machine Cycle 1 (MC1): Fetch PUSH opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Decrement SP by 1 and write high byte (e.g., IXH or IYH) to memory at SP.
- Machine Cycle 4 (MC4): Decrement SP by 1 and write low byte (e.g., IXL or IYL) to memory at SP.
Each machine cycle includes three T-states (T1, T2, T3), and memory control signals (such as MREQ, RD, WR) are active as needed during these cycles.
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