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ZiLOG eZ80 User Manual

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eZ80
CPU
User Manual
UM007714-0908
®
Copyright © 2008 by Zilog
, Inc. All rights reserved.
www.zilog.com

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Summary of Contents for ZiLOG eZ80

  • Page 1 ® eZ80 User Manual UM007714-0908 ® Copyright © 2008 by Zilog , Inc. All rights reserved. www.zilog.com...
  • Page 2 Z8, Z8 Encore!, eZ80, Z8 Encore! XP, Z8 Encore! MC, Crimzon, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. .
  • Page 3 ® eZ80 User Manual Revision History Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below. Revision Date Level Description...

  • Page 4: Table Of Contents

    ® eZ80 User Manual Table of Contents Manual Objectives ........... vi About This Manual .
  • Page 5 ® eZ80 User Manual Illegal Instruction Traps..........46 I/O Space.

  • Page 6: Manual Objectives

    This document is written for Zilog customers who are experienced at working with micro- controllers or in writing assembly code or compilers. Manual Organization The eZ80 CPU User Manual is divided into twelve sections; each section details a specific topic about the product. Introduction This chapter provides an introduction to eZ80 CPU, Zilog’s next-generation processor...

  • Page 7: Manual Conventions

    This chapter describes the MADL control bit and mixed memory mode guidelines. CPU Instruction Set This chapter lists assembly language instructions, including mnemonic definitions and a ® summary of the eZ80 CPU instruction set. Opcode Maps This chapter provides a detailed diagram of each opcode segment.
  • Page 8 ® eZ80 User Manual viii Courier Typeface Commands, code lines and fragments, bits, equations, hexadecimal addresses, and various executable items are distinguished from general text by the use of the typeface. Courier Where the use of the font is not indicated, as in the Index, the name of the entity is pre- sented in upper case.

  • Page 9: Safeguards

    ® eZ80 User Manual Use of the Terms LSB and MSB In this document, the terms LSB and MSB, when appearing in upper case, mean least sig- nificant byte and most significant byte, respectively. The lowercase forms, msb and lsb, mean least significant bit and most significant bit, respectively.

  • Page 10: Introduction

    Z80-compatible (64 KB) mode or full 24-bit (16 MB) address mode. The eZ80 CPU’s instruction set is a superset of the instruction sets for the Z80 and Z180 CPUs. The Z80 and Z180 programs are executed on an eZ80 CPU with little or no modifi- cation.

  • Page 11: Architectural Overview

    User Manual Architectural Overview ® The eZ80 CPU is Zilog's next-generation Z80 processor core. It is the basis of a new family of integrated microcontrollers and includes the following features: • Upward code-compatible from Z80 and Z180 products. •...

  • Page 12: Pipeline Description

    ® eZ80 User Manual and WRITEs. It also discards prefetched instructions when jumps, interrupts, and other control transfer events occur. Mode Control The Mode Control block of the CPU controls which mode the processor is currently oper- ating in: HALT mode, SLEEP mode, Interrupt mode, debug mode, and ADL mode Opcode Decoder The opcodes are decoded within the CPU control block.
  • Page 13 ® eZ80 User Manual while it executes the current instruction as displayed in Figure 2. The CPU operates on multiple instructions simultaneously to improve operating efficiency. System Clock Instruction 1 Fetch Decode Execute Instruction 2 Fetch Decode Execute Instruction 3...
  • Page 14 ® eZ80 User Manual Clock PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 PC+7 Address 1234h 5678h Data In (1234h) (5678h) INC A LD (nn), A LD (nn), A Write INC A Write Command Execution Next command Next command State 1 clock delay for execution...

  • Page 15: Memory Modes

    User Manual Memory Modes ® The eZ80 CPU is capable of operating in two memory modes: Z80 mode and ADL mode. For backward compatibility with legacy Z80 programs, the CPU operates in Z80 MEMORY mode with 16-bit addresses and 16-bit CPU registers. For 24-bit linear addressing and 24-bit CPU registers, the CPU operates in ADDRESS AND DATA LONG (ADL) mode.

  • Page 16: Adl Memory Mode

    ® eZ80 User Manual Memory MBASE Location 000000h Z80 Mode Page 0 64 KB 00FFFFh 010000h Z80 Mode Page 1 64 KB 01FFFFh 020000h Z80 Mode Page 2 64 KB 02FFFFh 8F0000h Z80 Mode Page 127 64 KB 8FFFFFh FE0000h...
  • Page 17 ® eZ80 User Manual set. When ADL mode is selected, MBASE does not affect memory addressing. Figure 5 displays the ADL mode memory map. Note: There are no pages in ADL mode. 24-Bit Memory Address Location 000000h 000000h ADL Mode...

  • Page 18: Registers And Bit Flags

    ® eZ80 User Manual Registers and Bit Flags ® eZ80 CPU Working Registers The CPU contains two banks of working registers—the main register set and the alternate register set. The main register set contains the 8-bit accumulator register (A) and six 8-bit working registers (B, C, D, E, H, and L).

  • Page 19: Ez80 ® Cpu Control Bits

    ® eZ80 User Manual • Program Counter (PC) register—the multibyte Program Counter register stores the address of the current instruction being fetched from memory. The Program Counter is automatically incremented during program execution. When a program jump occurs, the new value is placed in the Program Counter, overriding the incremented value. In Z80 mode, the Program Counter is only 16 bits;...

  • Page 20: Ez80 Cpu Registers In Z80 Mode

    ® eZ80 User Manual • Interrupt Enable Flags (IEF1 and IEF2)—in the CPU, there are two interrupt enable flags that are set or reset using the Enable Interrupt (EI) and Disable Interrupt (DI) instructions. When IEF1 is reset to 0, a maskable interrupt cannot be accepted by the CPU.

  • Page 21: Ez80 Cpu Registers In Adl Mode

    ® eZ80 User Manual Table 2. CPU Control Registers and Bit Flags in Z80 Mode 8-Bit 16-Bit Registers Registers Single-Bit Flags MBASE MADL IEF1 IEF2 16-Bit Individual 8-Bit Registers Registers ® eZ80 CPU Registers in ADL Mode In ADL mode, the BC, DE, HL, IX and IY registers are 24 bits long for multibyte opera- tions and indirect addressing.
  • Page 22 ® eZ80 User Manual Table 3. CPU Working Registers in ADL Mode Main Register Set Alternate Register Set 8-Bit 8-Bit Registers Registers A’ F’ 24-Bit 24-Bit Individual Register Individual Register 8-Bit Registers 8-Bit Registers BCU’ B’ C’ BC’ DEU’ D’...

  • Page 23: Ez80 Cpu Status Indicators (Flag Register)

    ® eZ80 User Manual Table 5. CPU Register and Bit Flag Reset States CPU Register or Bit Flag Reset State 8-Bit Working Registers A, A’ Undefined B, B’ Undefined C, C’ Undefined D, D’ Undefined E, E’ Undefined F, F’...
  • Page 24 ® eZ80 User Manual where: C = Carry Flag N = Add/Subtract Flag P/V = Parity/Overflow Flag H = Half-Carry Flag Z = 0 Flag S = Sign Flag X = Not used Each of the two CPU flag registers contain six bits of status information that are set or reset by CPU operations.
  • Page 25 ® eZ80 User Manual For addition, operands with different signs never causes overflow. When adding operands with like signs where the result yields a different sign, the overflow flag is set to 1, as indi- cated in Table Table 7. Overflow Flag Addition Settings...
  • Page 26 ® eZ80 User Manual Half-Carry Flag (H) The Half-Carry flag (H) is set or reset, depending on the carry and borrow status between bits 3 and 4 of an 8-bit arithmetic operation. This flag is used by the decimal adjust accu- mulator instruction (DAA) to correct the result of a packed BCD addition or subtraction.

  • Page 27: Memory Mode Switching

    Memory Mode Compiler Directives In the Zilog ZMASM/ZDS assembler, the application code is assembled for a given state of the ADL mode bit by placing one of the two following compiler directives at the top of the code: .ASSUME ADL = 1...
  • Page 28 ® eZ80 User Manual Each of the four suffixes .SIS, .SIL, .LIS, and .LIL is composed of 2 parts that define the operation in the control block and the data block within the CPU (see Figure 1 on page 2 Table 10).

  • Page 29: Single-Instruction Memory Mode Changes

    ;bits of data. .L uses all 3 bytes ;of HL register. LD.SIL HL, 123456h ;HL[23:0] ¨ {00h, 3456h}. ;.IL directs eZ80 to fetch 24 bits ;of data. .S forces upper byte of ;HL register to an undefined ;state because registers are ;defined to be only 16-bits.
  • Page 30 ;.L uses all 3 bytes of HL ;register. ;HL[23:0] ← {00h, 3456h}. LD.SIL HL, 123456h ;.IL directs eZ80 to fetch 24 bits ;of data. .S forces upper byte of HL ;register to an undefined state. From these two suffix examples, it can be seen that with the extensions applied, operation is consistent regardless of the persistent memory mode in operation at the time.
  • Page 31 ® eZ80 User Manual ;HL[23:0] ← {00h, 3456h}. LD.SIL HL, 123456h ;.IL directs eZ80 to fetch 24 bits ;of data. .S forces upper byte of ;HL register to an undefined ;state. A different value is ;stored in HL than expected.
  • Page 32 ® eZ80 User Manual ;already operating in Z80 Mode. ;The .IL portion of the suffix has ;no effect since instruction ;length is unambiguous. LD.LIS (HL), BC ;24-bit value stored in BC[23:0] ;is written to the 24-bit memory ;location given by HL[23:0]. The ;.L portion of the suffix forces...

  • Page 33: Suffix Completion By The Assembler

    ® eZ80 User Manual ;no effect because instruction ;length is unambiguous. LD.LIS (HL), BC ;24-bit value stored in BC[23:0] ;is written to the 24-bit memory ;location given by HL[23:0]. ;Because it is operating in ADL ;Mode, the.L portion of the suffix ;has no effect on this instruction...

  • Page 34: Persistent Memory Mode Changes In Adl And Z80 Modes

    , and , which indicate opcodes that ® are not on the first page of the opcode map. The eZ80 MEMORY mode prefix bytes ) must precede the traditional Z80 prefix bytes. Persistent Memory Mode Changes in ADL and Z80 Modes...
  • Page 35 ® eZ80 User Manual The memory mode can be changed by adding a suffix to a CALL, JP, RST, or RET, RETI, or, RETN instruction. Tables 14 through 20 describe how each of these 4 instruc- tions function. The individual instructions may perform additional operations that are not described here.
  • Page 36 ® eZ80 User Manual Table 14. CALL Mmn Instruction (Continued) Assembled User Code Mode Code Operation The starting program counter is {MBASE, CALL.IL CALL.SIL PC[15:0]}. Push the 2-byte logical return address, assembles to PC[15:0], onto the SPL stack. Push a 02h byte...
  • Page 37 ® eZ80 User Manual Table 15. JP Mmn Instruction (Continued) Assembled User Code Mode Code Operation The starting program counter is PC[23:0]. Write the JP Mmn JP Mmn assembles to 3-byte immediate value {MM, mm, nn}, to PC[23:0]. The ADL mode bit remains set to 1. The...
  • Page 38 ® eZ80 User Manual Table 16. JP (rr) Instruction (Continued) Assembled User Code Mode Code Operation The starting program counter is PC[23:0]. Write the JP (rr) JP (rr) assembles to 3-byte value stored in rr[23:0] to PC[23:0]. The E9 or DD/FD ADL mode bit remains set to 1.
  • Page 39 ® eZ80 User Manual Table 17. RST n Instruction (Continued) Assembled User Code Mode Code Operation The starting program counter is PC[23:0]. Push the RST.S n RST.SIL n assembles to 2 LS bytes of the return address, PC[15:0], onto the {MBASE, SPS} stack. Push the MS byte of the 52 CD nn return address, PC[23:16], onto the SPL stack.
  • Page 40 ® eZ80 User Manual Table 18. RET Instruction (Continued) Assembled User Code Mode Code Operation — An invalid suffix. RET.L must be used in all mixed- RET.S memory mode applications. The starting program counter is {MBASE, RET.L RET.LIS assembles to PC[15:0]}.
  • Page 41 ® eZ80 User Manual Table 19. RETI Instruction (Continued) Assembled User Code Mode Code Operation The starting program counter is PC[23:0]. Pop a 3- RETI RETI assembles to byte return address from SPL into PC[23:0]. The ADL mode bit remains set to 1. The ending ED 4D program counter is PC[23:0].
  • Page 42 ® eZ80 User Manual Table 20. RETN Instruction Assembled User Code Mode Code Operation The starting program counter is {MBASE, RETN RETN assembles to PC[15:0]}. Pop a 2-byte return address from {MBASE, SPS} into PC[15:0]. The ADL mode bit ED 45 remains cleared to 0.

  • Page 43: Mixed-Memory Mode Applications

    User Manual Mixed-Memory Mode Applications ® The eZ80 CPU contains a control bit flag that affects operation of interrupts, illegal instruction traps and restart (RST) instructions. The Mixed-ADL (MADL) control bit must be set to 1 for all applications that run in both Z80 mode and ADL mode. The MADL control bit can be reset to 0 for all CPU applications that run exclusively in Z80 mode or exclusively in ADL mode.
  • Page 44 In mixed-ADL applications, some of these rules may represent exceptions to the eZ80 ® CPU’s design goal; that legacy code does not require modification to run on the eZ80 CPU. Assuming that legacy routines are not selectively converted to ADL mode and do not call newly-written routines, the only rule that could lead to such modification is Rule 5.

  • Page 45: Interrupts

    Interrupt Enable Flags (IEF1 and IEF2) ® In the eZ80 CPU, there are two interrupt enable flags (IEF1 and IEF2) that are set or reset using the Enable Interrupt (EI) and Disable Interrupt (DI) instructions. When IEF1 is reset to 0 by a DI instruction, a maskable interrupt cannot be accepted by the CPU.

  • Page 46: Ez80 ® Cpu Response To A Nonmaskable Interrupt

    ® eZ80 User Manual begin in ADL mode. To explain, the ADL mode bit is set to 1 and full 24-bit linear addressing is used to access the ISRs. The ADL mode bit setting of the interrupted code is pushed onto the stack, using SPL, to allow the memory mode to return to the appropriate value after completion of the ISR.

  • Page 47: Ez80 Cpu Response To A Maskable Interrupt

    IM 0, IM 1, and IM 2 instructions. Not all products within the ® ® eZ80 family support all 3 of these interrupt modes. Refer to the eZ80 ® eZ80Acclaim! product specifications for information on supported interrupt modes.
  • Page 48 ® eZ80 User Manual Table 22. Interrupt Mode 0 Operation MADL Current Mode Control Operation (if RST n or CALL Mmn is placed on the Memory Mode data bus) Z80 mode Read the RST n of CALL mn instruction placed on the data bus, D[7:0], by the interrupting peripheral.
  • Page 49 ® eZ80 User Manual Table 22. Interrupt Mode 0 Operation (Continued) MADL Current Mode Control Operation (if RST n or CALL Mmn is placed on the Memory Mode data bus) ADL mode Read RST n or CALL Mmn instruction placed on the data bus, D[7:0], by interrupting peripheral.
  • Page 50 ® eZ80 User Manual Table 23. Interrupt Mode 1 Operation (Continued) MADL Current Mode Control Memory Mode Operation IEF1 ← 0 Z80 mode IEF2 ← 0 The starting program counter is {MBASE, PC[15:0]}. Push the 2-byte return address, PC[15:0], onto the SPL stack.
  • Page 51 ® eZ80 User Manual Table 24. Interrupt Mode 2 Operation MADL Memory Mode Operation Z80 Mode Read the LSB of the interrupt vector placed on the data bus, D[7:0], by the interrupting peripheral. IEF1 ← 0 • IEF2 ← 0 •...

  • Page 52: Vectored Interrupts For On-Chip Peripherals

    ® eZ80 User Manual Table 24. Interrupt Mode 2 Operation (Continued) MADL Memory Mode Operation Z80 Mode Read the LSB of the interrupt vector placed on the data bus, D[7:0], bus by the interrupting peripheral. IEF1 ← 0 • IEF2 ← 0 •...
  • Page 53 8-bit I register, an 8-bit ® ® IVECT, and a 16-bit word fetch in ADL modes. Refer to the eZ80 and eZ80Acclaim! product specifications for information on product specific vectored interrupt modes.
  • Page 54 ® eZ80 User Manual Table 25. Vectored Interrupt Operation (Continued) MADL Memory Mode Operation Z80 Mode Read the LSB of the interrupt vector placed on the internal vectored interrupt bus, IVECT[8:0], bus by the interrupting peripheral. IEF1 ← 0 •...

  • Page 55: Illegal Instruction Traps

    Some products that employ the CPU can also contain a TRAP register for capturing the ® ® illegal binary value. Refer to the eZ80 and eZ80Acclaim! product specifications for more information. UM007714-0908...

  • Page 56: I/O Space

    I/O Space ® A separate I/O space may include both on- and off-chip peripheral devices. The eZ80 CPU is capable of addressing a 64 KB I/O space with 16-bit addresses. The memory and I/ O space share the same 24-bit address and 8-bit data buses. However, the I/O peripherals are accessed using special I/O instructions including IN, OUT, and TSTIO.

  • Page 57: Addressing Modes

    User Manual Addressing Modes ® The eZ80 CPU instruction set includes many different memory addressing modes. The memory address can be formed using several different methods, as outlined in the follow- ing text. The addressing modes supported are a function of each instruction.
  • Page 58 ® eZ80 User Manual BC (16- or 24-Bit) DE (16- or 24-Bit) Operand HL (16- or 24-Bit) Memory Space Figure 6. Register Indirect Addressing Immediate Addressing The memory operands immediately follows the instruction. The memory operand can be 8, 16, or 24 bits, depending on the instruction and the memory mode in use. Immediate...
  • Page 59 ® eZ80 User Manual Indexed Addressing In this mode of addressing, a byte of data following the opcode contains a displacement to be added to one of the IX or IY Index registers. The displacement is a two’s-complement value in the range +127 to –128.
  • Page 60 ® eZ80 User Manual instruction. The displacement can range from +127 to –128. Figure 10 displays the rela- tive addressing. Op Code 1 Displacement (d) Program Counter (PC) Figure 10. Relative Addressing I/O Addressing I/O addressing mode is used only by the I/O instructions IN and OUT. See I/O Space page 47 for more information on I/O operations.

  • Page 61: Cpu Instruction Set

    ® eZ80 User Manual CPU Instruction Set ® eZ80 CPU Assembly Language Programming Introduction ® eZ80 CPU assembly language provides a means for writing an application program without considering the actual memory addresses or machine instruction formats. A program written in assembly language is called a source program. Assembly language allows the use of symbolic addresses to identify memory locations.

  • Page 62: Ez80 ® Cpu Instruction Notations

    ® eZ80 User Manual description of instruction operands. The nomenclature is defined with special emphasis on mnemonic values and readability. The movement of data is indicated by a single opcode, regardless whether the movement is between different registers or between registers and memory locations. For example, the first operand of an LD instruction is the destination of the operation and the second operand is the source of the operation.

  • Page 63: Ez80 ® Cpu Instruction Classes

    ® eZ80 User Manual Table 26. Instruction Notations (Continued) Mnemonic Definition A 24-bit immediate data value A 24-bit value indicating a location in memory at this (Mmn) address A 16-bit immediate data value A 16-bit value indicating a location in memory at this...
  • Page 64 ® eZ80 User Manual Table 28. Bit Manipulation Instructions Mnemonic Instruction Page(s) Bit Test 106–110 Reset Bit 288–291 Set Bit 339–342 Table 29. Block Transfer and Compare Instructions Mnemonic Instruction Page(s) Compare and Decrement (with 124–125 CPD (CPDR) Repeat) Compare and Increment (with 126–127...
  • Page 65 ® eZ80 User Manual Table 31. Input/Output Instructions (Continued) Mnemonic Instruction Page(s) Input from I/O and Decrement (with 167–168 INDM (INDMR) Repeat) Input from I/O and Increment (with INI (INIR) Repeat) Input from I/O and Increment INIRX Memory Address with Stationary I/O...
  • Page 66 ® eZ80 User Manual Table 32. Load Instructions Mnemonic Instruction Page(s) Load 189–237 Load Effective Address 242–245 Push Effective Address 275–276 277–280 Push PUSH 282–286 Table 33. Logical Instructions Mnemonic Instruction Page(s) Logical AND 100–104 Complement Accumulator Logical OR 250–254 Test Accumulator 363–365...
  • Page 67 ® eZ80 User Manual Table 35. Program Control Instructions Mnemonic Instruction Page(s) Call Subroutine CALL Conditional Call Subroutine CALL cc Decrement and Jump if Nonzero DJNZ Jump 182–185 Conditional Jump JP cc Jump Relative Conditional Jump Relative JR cc Return...

  • Page 68: Instruction Summary

    ® eZ80 User Manual Instruction Summary Table 37 describes each type or class of instruction, using the notation described in the preceding sections. In addressing modes where the same location acts as both the destination (Dest) and the source (Source), the information is centered between the Dest and Source columns (for example, the DEC instruction).
  • Page 69 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N BIT b,s (HL) — CB 46–7E Z ← ~s[b] (IX/Y+d) DD/FD CB dd 46–7E CB 40–7F CALL cc,Mmn —...
  • Page 70 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N — ED A1 A–(HL) HL ← HL+1 BC ← BC – 1 CPIR — ED B1 repeat { A–(HL)
  • Page 71 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N EX AF,AF’ AF ↔ AF’ EX DE,HL — — — — — — DE ↔ HL EX (SP),ss —...
  • Page 72 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N IND2 — — — — ED 8C (HL) ← ({00h, BC[15:0]}) B ← B – 1 C ← C – 1 HL ←...
  • Page 73 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N INDRX — — — — ED CA repeat { (HL) ← ({00h, DE[15:0]}) BC ← BC – 1 HL ←...
  • Page 74 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N INIMR — — — — ED 92 repeat { (HL) ← ({0000h, C}) B ← B – 1 C ←...
  • Page 75 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N JR cc’,d — — — — — — 20–38 if cc’ {PC ← PC+d} JR d — — —...
  • Page 76 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N LD (IX/Y+d), ss IX/Y DD/FD 3E-3F — — — — — — (IX/Y+d) ← ss DD/FD 36 DD/FD 70-77 DD/FD 0F–2F...
  • Page 77 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N — — — ED A8 (DE) ← (HL) DE ← DE – 1 HL ← HL – 1 BC ←...
  • Page 78 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N MLT ss — — — — — — ED 4C–6C ss[15:0] ← ss[15:8] X ss[7:0] ED 7C ED 44 A ←...
  • Page 79 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N OTDR — — — — ED BB repeat { ({00h, BC[15:0]}) ← (HL) B ← B – 1 HL ←...
  • Page 80 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N OTIR — — — — ED B3 repeat { ({00h, BC[15:0]}) ← (HL) B ← B – 1 HL ←...
  • Page 81 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N OUTI2 — — — — ED A4 ({00h, BC[15:0]}) ← (HL) B ← B – 1 C ← C+1 HL ←...
  • Page 82 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N PUSH ss — — — — — — if ADL mode { IX/Y DD/FD E5 (SPL) ← ss C5-E5 SPL ←...
  • Page 83 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N RLC s (HL) CB 06 (IX/Y+d) DD/FD CB dd CB 00-07 RLCA — — — — ED 6F A[3:0] ←...
  • Page 84 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N RRC s (HL) CB 1E (IX/Y+d) DD/FD CB dd CB 08-0F RRCA — — — — ED 67 A[3:0] ←...
  • Page 85 ® eZ80 User Manual Table 37. Instruction Summary (Continued) Address Mode Flags Affected Opcode(s) Instruction and Operation Dest Source (Hex) H P/V N SBC HL, ss ED 42-62 HL ← HL – ss – C ED 72 — — —...

  • Page 86: Ez80 ® Cpu Instruction Set Description

    CPU. Some CPU-based products may not support all instruc- ® ® tions, registers, operating modes, etc. Refer to the eZ80 and eZ80Acclaim! product specifications for information on CPU usage. The instruction set descriptions on the fol- lowing pages are organized alphabetically by mnemonic.
  • Page 87 ® eZ80 User Manual cycles required to execute the instruction is a function of the number of bus cycles, the number of wait states in use, and whether or not conditional operations are performed. UM007714-0908 CPU Instruction Set...
  • Page 88 ® eZ80 User Manual ADC A, (HL) ADD with Carry Operation A ← A+(HL)+C Description The (HL) operand is an 8-bit value retrieved from the memory location specified by the contents of the multibyte register HL. This 8-bit value and the Carry Flag (C) are added to the contents of the accumulator, A.
  • Page 89 ® eZ80 User Manual ADC A, ir ADD with Carry Operation A ← A+ir+C Description The ir operand is any of the 8-bit registers IXH, IXL, IYH, or IYL. The ir operand and the Carry Flag (C) are added to the contents of the accumulator, A. The result is stored in the accumulator.
  • Page 90 ® eZ80 User Manual ADC A, (IX/Y+d) ADD with Carry Operation A ← A+(IX/Y+d)+C Description (IX/Y+d) is an 8-bit value stored in the memory location specified by the Index Register, IX or IY, offset by the two’s-complement displacement d. This 8-bit value and the Carry Flag (C) are added to the contents of the accumulator, A.
  • Page 91 ® eZ80 User Manual ADC A, n ADD with Carry Operation A ← A+ Description The 8-bit immediate value n and the Carry Flag (C) are added to the contents of the accu- mulator, A. The result is stored in the accumulator.
  • Page 92 ® eZ80 User Manual ADC A, r ADD with Carry Operation A ← A+r+C Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The r operand and the Carry Flag (C) are added to the contents of the accumulator, A. The result is stored in the accumulator.
  • Page 93 ® eZ80 User Manual Table 38. Register and jj Opcodes for ADC A, r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 94 ® eZ80 User Manual ADC HL, rr ADD with Carry Operation HL ← HL+rr+C Description The rr operand is any of the multibyte registers BC, DE, or HL. The rr operand and the Carry Flag (C in the F register) are added to the contents of the HL register. The result is stored in the HL register.
  • Page 95 ® eZ80 User Manual Table 39. Register and kk Opcodes for ADC HL, rr instruction (hex) Register kk UM007714-0908 CPU Instruction Set...
  • Page 96 ® eZ80 User Manual ADC HL, SP ADD with Carry Operation HL ← HL+SP+C Description The Stack Pointer and the Carry Flag (C in the F register) are added to the contents of the HL register. The result is stored in the HL register. In ADL mode, or when the .L suffix is employed, SPL is used for SP.
  • Page 97 ® eZ80 User Manual ADD A, (HL) ADD without Carry Operation A ← A+(HL) Description The (HL) operand is an 8-bit value retrieved from the memory location specified by the contents of the multibyte register HL. This 8-bit value is added to the contents of the accu- mulator, A.
  • Page 98 ® eZ80 User Manual ADD A, ir ADD without Carry Operation A ← A+ir Description The ir operand is any of IXH, IXL, IYH, or IYL. The ir operand is added to the contents of the accumulator, A. The result is stored in the accumulator.
  • Page 99 ® eZ80 User Manual ADD A, (IX/Y+d) ADD without Carry Operation A ← A+(IX/Y+d) Description The (IX/Y+d) operand is an 8-bit value retrieved from the memory location specified by the contents of the Index Register, IX or IY, offset by the two’s complement displacement d.
  • Page 100 ® eZ80 User Manual ADD A, n ADD without Carry Operation A ← A+n Description The 8-bit immediate value n is added to the contents of the accumulator, A. The result is stored in the accumulator. Condition Bits Affected Set if result is negative; reset otherwise.
  • Page 101 ® eZ80 User Manual ADD A, r ADD without Carry Operation A ← A+r Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The r operand is added to the contents of the accumulator, A. The result is stored in the accumulator.
  • Page 102 ® eZ80 User Manual Table 40. Register and jj Opcodes for ADD A, r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 103 ® eZ80 User Manual ADD HL, rr ADD without Carry Operation HL ← HL+rr Description The rr operand is any of the multibyte registers BC, DE, or HL. The CPU adds the con- tents of the rr register to the contents of the HL register, and stores the results in the HL register.
  • Page 104 ® eZ80 User Manual Table 41. Register and kk Opcodes for ADD HL, rr Instruction (hex) Register kk UM007714-0908 CPU Instruction Set...
  • Page 105 ® eZ80 User Manual ADD HL, SP ADD without Carry Operation HL ← HL+SP Description The CPU adds the contents of the multibyte Stack Pointer (SP) register to the contents of the HL register, and stores the results in the HL register. In ADL mode, or when the .L suf- fix is employed, SPL is used for SP.
  • Page 106 ® eZ80 User Manual ADD IX/Y, rxy ADD without Carry Operation IX/Y ← IX/Y+rxy Description The rxy operand is any of the multibyte BC, DE, or IX/Y registers. The CPU adds the contents of the multibyte register rxy to the contents of the Index Register, IX or IY, and stores the results in the Index Register, IX or IY.
  • Page 107 ® eZ80 User Manual Table 42. Register and kk Opcodes for ADD IX/Y, rxy Instruction (hex) Register kk IX/IY 29 (destination is the same as the source) IX ← IX+IX or IY ← IY+IY UM007714-0908 CPU Instruction Set...
  • Page 108 ® eZ80 User Manual ADD IX/Y, SP ADD without Carry Operation IX/Y ← IX/Y+SP Description The CPU adds the contents of the multibyte Stack Pointer register (SP) to the contents of the Index Register, IX or IY, and stores the results in the Index Register, IX or IY. In ADL mode, or when the .L suffix is employed, SPL is used for SP.
  • Page 109 ® eZ80 User Manual AND A, (HL) Logical AND Operation A ← A AND (HL) Description The (HL) operand is the 8-bit value stored at the memory location indicated by the con- tents of the multibyte HL register. This 8-bit value is bitwise ANDed with the contents of the accumulator, A.
  • Page 110 ® eZ80 User Manual AND A, ir Logical AND Operation A ← A AND ir Description The ir operand is any of the 8-bit registers IXH, IXL, IYH, or IYL. The ir operand is bit- wise ANDed with the contents of the accumulator, A. The result is stored in the accumula- tor.
  • Page 111 ® eZ80 User Manual AND A, (IX/Y+d) Logical AND Operation A ← A AND (IX/Y+d) Description The (IX/Y+d) operand is the 8-bit value stored in the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d.
  • Page 112 ® eZ80 User Manual AND A, n Logical AND Operation A ← A AND n Description The 8-bit immediate value n is bitwise ANDed with the contents of the accumulator, A. The result is stored in the accumulator. Condition Bits Affected Set if result is negative;...
  • Page 113 ® eZ80 User Manual AND A, r Logical AND Operation A ← A AND r Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The r operand is bitwise ANDed with the contents of the accumulator, A. The result is stored in the accu- mulator.
  • Page 114 ® eZ80 User Manual Table 43. Register and jj Opcodes for AND A, r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 115 ® eZ80 User Manual Bit b, (HL) Bit Test Operation Z ← ~(HL)[b] Description The (HL) operand is an 8-bit value stored at the memory location specified by the contents of the multibyte register HL. This instruction tests bit b of this 8-bit value and sets the 0 Flag (Z) if the bit is 0.
  • Page 116 ® eZ80 User Manual Table 44. Bit tested, bb values, and kk Opcode for Bit B, (HL) Instruction (hex) UM007714-0908 CPU Instruction Set...
  • Page 117 ® eZ80 User Manual Bit b, (IX/Y+d) Bit Test Operation Z ← ~(IX/Y+d)[b] Description The (IX/Y+d) operand is an 8-bit value stored at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d.
  • Page 118 ® eZ80 User Manual Table 45. Bit test, bb, and Opcodes for Bit B, (IX/Y+d) Instruction (hex) Register bb UM007714-0908 CPU Instruction Set...
  • Page 119 ® eZ80 User Manual Bit b, r Bit Test Operation ← Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. This instruction tests bit b in the specified register and sets the 0 Flag (Z) if the bit is 0. The Z Flag is reset if bit b of register r is a one.
  • Page 120 ® eZ80 User Manual Table 46. Register, bbb, and rrr Opcodes for Bit b, r Instruction (hex) Bit Tested Register UM007714-0908 CPU Instruction Set...
  • Page 121 ® eZ80 User Manual CALL cc, Mmn Conditional CALL Subroutine Operation if cc { (SP) ← PC PC ← Mmn Description If condition cc is true (1), the return address is pushed onto the stack. The return address is the address of the instruction immediately following this CALL instruction. The Program Counter (PC) is loaded with the Mmn operand, and execution continues at the new PC address.
  • Page 122 ® eZ80 User Manual Table 47. Conditional Operations for CALL cc, Mmn Instruction (Continued) The starting Program Counter is PC[23:0]. Push the 2 LS bytes of the return address, PC[15:0], onto the {MBASE, SPS} stack. Push the MS byte of the return address, PC[23:16], onto the SPL stack.
  • Page 123 ® eZ80 User Manual Table 48. Opcode Assembly for CALL cc, Mmn Instruction (hex) Condition Relevant Flag Opcode NZ (non 0) Z (0) NC (no carry) C (carry) PO (parity odd) PE (parity even) P (sign positive) M (sign negative/minus)
  • Page 124 ® eZ80 User Manual CALL Mmn CALL Subroutine Operation (SP) ← PC PC ← Mmn Description The return address is pushed onto the stack. The return address is the address of the instruction immediately following this CALL instruction. Then the Program Counter (PC) is loaded with the Mmn operand and execution continues at the new PC address.
  • Page 125 ® eZ80 User Manual Table 49. Detail of the CALL Mmn Instruction The starting Program Counter is PC[23:0]. Push the 2 LS bytes of the return address, PC[15:0], onto the {MBASE, SPS} stack. Push the MS byte of the return address, PC[23:16], onto the SPL stack.
  • Page 126 ® eZ80 User Manual Complement Carry Flag Operation C ← ~C Description The Carry Flag bit (C) in the F register is inverted. Condition Bits Affected Not affected. Not affected. Previous carry is copied. Not affected. Reset. Set if carry was cleared to 0 before operation; reset otherwise.
  • Page 127 ® eZ80 User Manual CP A, (HL) Compare with Accumulator Operation A–(HL) Description The (HL) operand is an 8-bit value stored at the memory location specified by the contents of the multibyte register HL. This 8-bit value is compared with (subtracted from) the con- tents of the accumulator, A.
  • Page 128 ® eZ80 User Manual CP A, ir Compare with Accumulator Operation A – ir Description The ir operand is any of the 8-bit registers IXH, IXL, IYH, or IYL. The ir operand is com- pared with (subtracted from) the contents of the accumulator, A. The execution of this instruction does not affect the contents of the accumulator or the ir operand.
  • Page 129 ® eZ80 User Manual CP A, (IX/Y+d) Compare with Accumulator Operation A–(IX/Y+d) Description The (IX/Y+d) operand is the 8-bit value stored in the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d.
  • Page 130 ® eZ80 User Manual CP A, n Compare with Accumulator Operation A – n Description The 8-bit immediate value n is compared with (subtracted from) the contents of the accu- mulator, A. The execution of this instruction does not affect the contents of the accumula- tor.
  • Page 131 ® eZ80 User Manual CP A, r Compare with Accumulator Operation A – r Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The CPU compares the r operand to the contents of the accumulator, A, and outputs the difference. The execu- tion of this instruction does not affect the contents of the accumulator or the r operand.
  • Page 132 ® eZ80 User Manual Table 50. Register and jj Opcodes for CP A, r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 133 ® eZ80 User Manual Compare and Decrement Operation A–(HL) HL ← HL – 1 BC ← BC – 1 Description The CPU compares the contents of the accumulator, A, to the memory location that the HL register points to, and outputs the difference. This instruction does not affect the con- tents of the reference memory location or the accumulator.
  • Page 134 ® eZ80 User Manual CPDR Compare and Decrement with Repeat Operation repeat { A–(HL) HL ← HL – 1 BC ← BC – 1 } while (~Z and BC ≠ 0) Description The CPU compares the contents of the accumulator, A, to the memory location that the HL register points to and outputs the difference.
  • Page 135 ® eZ80 User Manual Compare and Increment Operation A–(HL) HL ← HL+1 BC ← BC – 1 Description The CPU compares the contents of the accumulator, A, to the memory location that the HL register points to and outputs the difference. This instruction does not affect the con- tents of the reference memory location or the accumulator.
  • Page 136 ® eZ80 User Manual CPIR Compare and Increment with Repeat Operation repeat { A–(HL) HL ← HL+1 BC ← BC – 1 } while (~Z and BC ≠ 0) Description The CPU compares the contents of the accumulator, A, to the memory location that the HL register points to and outputs the difference.
  • Page 137 ® eZ80 User Manual Complement Accumulator Operation A ← ~A Description All bits in the accumulator, A, are inverted (1’s complemented). Condition Bits Affected Not affected. Not affected. Set. Not affected. Set. Not affected. Attributes Mnemonic Operand ADL Mode Cycle Opcode (hex) —...
  • Page 138 ® eZ80 User Manual Decimal Adjust Accumulator Operation A ← Decimal Adjust (A) Description This instruction conditionally adjusts the accumulator, A, following addition and subtrac- tion operations on binary-coded-decimal (BCD) values. For addition (ADD, ADC, INC) or subtraction (SUB, SBC, DEC, NEG),...
  • Page 139 ® eZ80 User Manual Set if the msb of the result is 1 after the operation; reset otherwise. Set if the result is even parity after the operation; reset otherwise. Not affected. on page 129. Table 51 Attributes Mnemonic Operand...
  • Page 140 ® eZ80 User Manual Before operating, the DAA instruction checks the Carry Flag (C) and the Half-Carry Flag (H) to determine if a decimal adjustment is required as a result of the preceding BCD arithmetic operation. UM007714-0908 CPU Instruction Set...
  • Page 141 ® eZ80 User Manual DEC (HL) Decrement Operation (HL) ← (HL)–1 Description: The (HL) operand is an 8-bit value stored at the memory location specified by the contents of the multibyte register HL. This 8-bit value is decremented by 1.
  • Page 142 ® eZ80 User Manual DEC ir Decrement Operation ir ← ir – 1 Description: The ir operand is any of 8-bit CPU registers IXH, IXL, IYH, or IYL. The value contained in the specified register is decremented by 1. Condition Bits Affected Set if result is negative;...
  • Page 143 ® eZ80 User Manual DEC IX/Y Decrement Operation IX/Y ← IX/Y – 1 Description The value contained in the specified Index Register, IX or IY, is decremented by 1. Condition Bits Affected None. Attributes Mnemonic Operand ADL Mode Cycle Opcode (hex) DD, 2B DEC.S...
  • Page 144 ® eZ80 User Manual DEC (IX/Y+d) Decrement Operation (IX/Y+d) ← (IX/Y+d)–1 Description: The (IX/Y+d) operand is the 8-bit value stored in the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d.
  • Page 145 ® eZ80 User Manual DEC r Decrement Operation r ← r – 1 Description: The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The value contained in the specified register is decremented by 1.
  • Page 146 ® eZ80 User Manual Table 52. Register and jj Opcodes for DEC r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 147 ® eZ80 User Manual DEC rr Decrement Operation rr ← rr – 1 Description The rr operand is any of the multibyte CPU registers BC, DE, or HL. The value contained in the specified register is decremented by 1. Condition Bits Affected None.
  • Page 148 ® eZ80 User Manual DEC SP Decrement Operation SP ← SP – 1 Description The value contained in the Stack Pointer (SP) register is decremented by 1. In ADL mode, or when the .L suffix is employed, SPL is used for SP. In Z80 mode, or when the .S suffix is employed, the SPS is used for SP.
  • Page 149 ® eZ80 User Manual Disable Interrupt Operation IEF1 ← 0 IEF2 ← 0 Description: This instruction disables the maskable interrupts by resetting the interrupt enable flags (IEF1 and IEF2). Condition Bits Affected None. Attributes Mnemonic Operand ADL Mode Cycle Opcode (hex) —...
  • Page 150 ® eZ80 User Manual DJNZ d Decrement B Jump not 0 Operation B ← B – 1 if B ≠ 0 { PC ← PC+d Description The B register decrements by 1. If the resultant value in register B is not 0, the two’s-com- plement displacement d is added to the value of the Program Counter.
  • Page 151 ® eZ80 User Manual Enable Interrupt Operation IEF1 ← 1 IEF2 ← 1 Description This instruction sets the interrupt enable flags (IEF1 and IEF2) to a logical 1, which allows any maskable interrupt to be recognized. Condition Bits Affected None.
  • Page 152 ® eZ80 User Manual EX AF, AF’ Exchange AF and AF’ Operation A ↔ A’ F ↔ F’ Description The CPU exchanges the contents of the accumulator, A, and the Flag register, F, with the contents of the alternate accumulator, A’, and alternate Flag register, F’, respectively.
  • Page 153 ® eZ80 User Manual EX DE, HL Exchange DE with HL Operation DE ↔ HL Description The CPU exchanges the contents of the DE register with the contents of the HL register. Condition Bits Affected None. Attributes Mnemonic Operand ADL Mode...
  • Page 154 ® eZ80 User Manual EX (SP), HL Exchange Stack and HL Register Operation if ADL = 1 { (SPL) ↔ HL[7:0] (SPL+1) ↔ HL[15:8] (SPL+2) ↔ HL[23:16] else if ADL = 0 { SPS ↔ HL[7:0] (SPS+1) ↔ HL[15:8] Description The CPU exchanges the contents of the multibyte CPU register HL with the contents of the memory location specified by the Stack Pointer (SP).
  • Page 155 ® eZ80 User Manual EX (SP), IX/Y Exchange Stack and Index Register Operation if ADL = 1 { (SPL) ↔ IX/Y[7:0] (SPL+1) ↔ IX/Y[15:8] (SPL+2) ↔ IX/Y[23:16] else if ADL = 0 { SPS ↔ IX/Y[7:0] (SPS+1) ↔ IX/Y[15:8] Description The CPU exchanges the contents of the multibyte Index Register, IX or IY, with the mem- ory location specified by the Stack Pointer (SP).
  • Page 156 ® eZ80 User Manual Exchange Working Register Set with Alternate Register Set Operation BC ↔ BC’ DE ↔ DE’ HL ↔ HL’ Description The CPU exchanges the contents of the primary working registers BC, DE, and HL with the alternate working registers BC’, DE’, and HL’, respectively.
  • Page 157 ® eZ80 User Manual HALT Halt Operation while HALT { Description The HALT instruction suspends CPU operation until a subsequent interrupt or reset is received. While in HALT mode, the CPU executes NOPs. The Program Counter, PC, stops incrementing while in HALT mode.
  • Page 158 Mnemonic Operand ADL Mode Cycle Opcode (hex) ED, 46 ED, 56 ED, 5E Attributes ® Not all eZ80 products support the three interrupt modes. Refer to the individual product specification for information on supported interrupt modes. UM007714-0908 CPU Instruction Set...
  • Page 159 ® eZ80 User Manual IN A, (n) Input from I/O Operation A ← ({UU, A, n}) Description The n operand is placed on the lower byte of the address bus, ADDR[7:0]; the contents of the accumulator, A, are placed on the middle byte of the address bus, ADDR[15:8]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses.
  • Page 160 ® eZ80 User Manual IN r, (BC)—also IN r, (C) for Z80 compatibility Input from I/O Operation r ← ({UU, BC[15:0]}) Description The CPU places the contents of the 16-bit BC multibyte register onto the lower two bytes of the address bus at ADDR[15:0]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses.
  • Page 161 ® eZ80 User Manual Table 54. Register and jj Opcodes for IN , (BC) and IN r, (C) Instructions (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 162 ® eZ80 User Manual IN0 r, (n) Input from I/O Operation r ← ({UU, 00h, n}) Description The n operand is placed on the lower byte of the address bus, ADDR[7:0], while the High byte of the address bus, ADDR[15:8], is forced to 0. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses.The byte at this I/O address is written to the...
  • Page 163 ® eZ80 User Manual Table 55. Register and jj Opcodes for IN0 r, (n) Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 164 ® eZ80 User Manual INC (HL) Increment Operation (HL) ← (HL)+1 Description The (HL) operand is an 8-bit value stored at the memory location specified by the contents of the multibyte register HL. This 8-bit value increments by 1. Condition Bits Affected Set if result is negative;...
  • Page 165 ® eZ80 User Manual INC ir Increment Operation ir ← ir+1 Description The ir operand is any of the 8-bit CPU registers IXH, IXL, IYH, IYL. The contents of the specified register increment by 1. Condition Bits Affected Set if result is negative; reset otherwise.
  • Page 166 ® eZ80 User Manual INC IX/Y Increment Operation IX/Y ← IX/Y+1 Description The CPU increments the contents of the specified Index Register, IX or IY, by 1. In Z80 ← 00h mode, or when the .S suffix is employed, IX/Y[23:16] Condition Bits Affected None.
  • Page 167 ® eZ80 User Manual INC (IX/Y+d) Increment Operation (IX/Y+d) ← (IX/Y+d)+1 Description The (IX/Y+d) operand is an 8-bit register at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d. The CPU increments the contents of this 8-bit register by 1.
  • Page 168 ® eZ80 User Manual INC r Increment Operation r ← r+1 Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The CPU incre- ments the contents of the specified register r by 1.
  • Page 169 ® eZ80 User Manual Table 56. Register and jj Opcodes for INC r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 170 ® eZ80 User Manual INC rr Increment Operation rr ← rr+1 Description The rr operand is any of the multibyte CPU registers BC, DE, or HL. The CPU incre- ments the contents of the specified register by 1. In Z80 mode, or when the .S suffix is ←...
  • Page 171 ® eZ80 User Manual INC SP Increment Operation SP ← SP+1 Description The CPU increments the contents of the Stack Pointer register (SP) by 1. In ADL mode, or when the .L suffix is employed, SPL is used for SP. In Z80 mode, or when the .S suffix is employed, SPS is used for SP.
  • Page 172 ® eZ80 User Manual Input from I/O and Decrement Operation (HL) ← ({UU, BC[15:0]}) B ← B – 1 HL ← HL – 1 Description The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus, ADDR[15:0].
  • Page 173 ® eZ80 User Manual IND2 Input from I/O and Decrement Operation (HL) ← ({UU, BC[15:0]}) B ← B – 1 C ← C – 1 HL ← HL – 1 Description The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus, ADDR[15:0].
  • Page 174 ® eZ80 User Manual IND2R Input from I/O and Decrement with Repeat Operation repeat { (HL) ← ({UU, DE[15:0]}) BC ← BC – 1 DE ← DE – 1 HL ← HL – 1 } while BC ≠ 0 Description The CPU places the contents of DE[15:0] onto the lower two bytes of the address bus, ADDR[15:0].
  • Page 175 ® eZ80 User Manual Note This instruction operates differently in eZ80190 device. In the eZ80190, operation is: repeat { (HL) ← ({UU, BC[15:0]}) B ← B – 1 C ← C–1 HL ← HL–1 } while B ≠ 0 UM007714-0908...
  • Page 176 ® eZ80 User Manual INDM Input from I/O and Decrement Operation (HL) ← ({UU, 00h, C}) B ← B – 1 C ← C – 1 HL ← HL – 1 Description The CPU places the contents of register C onto the lower byte of the address bus, ADDR[7:0].
  • Page 177 ® eZ80 User Manual INDMR Input from I/O and Decrement with Repeat Operation repeat { (HL) ← ({UU, 00h,C}) B ← B – 1 C ← C – 1 HL ← HL – 1 } while B ≠ 0 Description The CPU places the contents of register C onto the lower byte of the address bus, ADDR[7:0], and places a 0 onto the High byte of the address bus, ADDR[15:8].
  • Page 178 ® eZ80 User Manual INDR Input from I/O and Decrement with Repeat Operation repeat { (HL) ← ({UU, BC[15:0]}) B ← B – 1 HL ← HL – 1 } while B ≠ 0 Description The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus, ADDR[15:0].
  • Page 179 ® eZ80 User Manual INDRX Input from I/O and Decrement Memory Address with Stationary I/O Address Operation repeat { (HL) ← ({UU, DE[15:0]}) BC ← BC – 1 HL ← HL – 1 } while BC ≠ 0 Description The CPU places the contents of register DE onto the lower byte of the address bus, ADDR[15:0].
  • Page 180 ® eZ80 User Manual Input from I/O and Increment Operation (HL) ← ({UU, BC[15:0]}) B ← B – 1 HL ← HL+1 Description The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus, ADDR[15:0]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses.
  • Page 181 ® eZ80 User Manual INI2 Input from I/O and Increment Operation (HL) ← ({UU, BC[15:0}) B ← B – 1 C ← C+1 HL ← HL+1 Description The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus, ADDR[15:0].
  • Page 182 ® eZ80 User Manual INI2R Input from I/O and Increment with Repeat Operation repeat { (HL) ← ({UU, DE[15:0]}) BC ← BC – 1 DE ← DE+1 HL ← HL+1 } while BC ≠ 0 Description The CPU places the contents of DE[15:0] onto the lower two bytes of the address bus, ADDR[15:0], and places a 0 onto the upper byte of the address bus, ADDR[23:16].
  • Page 183 ® eZ80 User Manual Note This instruction operates differently in eZ80190 device. In the eZ80190, operation is: repeat { (HL) ← ({UU, BC[15:0]}) B ← B – 1 C ← C+1 HL ← HL+1 } while B ≠ 0 UM007714-0908...
  • Page 184 ® eZ80 User Manual INIM Input from I/O and Increment Operation (HL) ← ({UU, 00h, C}) B ← B – 1 C ← C+1 HL ← HL+1 Description The CPU places the contents of register C onto the lower byte of the address bus, ADDR[7:0], and places a 0 onto the High byte of the address bus, ADDR[15:8].
  • Page 185 ® eZ80 User Manual INIMR Input from I/O and Increment with Repeat Operation repeat { (HL) ← ({UU, 00h, C}) B ← B – 1 C ← C+1 HL ← HL+1 } while B ≠ 0 Description The CPU places the contents of register C onto the lower byte of the address bus, ADDR[7:0], and places a 0 onto the High byte of the address bus, ADDR[15:8].
  • Page 186 ® eZ80 User Manual INIR Input from I/O and Increment with Repeat Operation repeat { (HL) ← ({UU, BC[15:0]}) B ← B – 1 HL ← HL+1 } while B ≠ 0 Description The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus, ADDR[15:0].
  • Page 187 ® eZ80 User Manual INIRX Input from I/O and Increment Memory Address with Stationary I/O Address Operation repeat { (HL) ← ({UU, DE[15:0]}) BC ← BC – 1 HL ← HL + 1 } while BC ≠ 0 Description The CPU places the contents of register DE onto the lower byte of the address bus, ADDR[15:0].
  • Page 188 ® eZ80 User Manual UM007714-0908 CPU Instruction Set...
  • Page 189 ® eZ80 User Manual JP cc, Mmn Conditional Jump Operation PC ← Mmn Description If the condition is true (a logical 1), the Program Counter, PC, is loaded with the instruc- tion operand. When assembled, the first byte after the opcode is the low-order byte of the operand.
  • Page 190 ® eZ80 User Manual Attributes Mnemonic Operand ADL Mode Cycle Opcode (hex) cc,mn kk, nn, mm cc,Mmn kk, nn, mm, MM JP.SIS cc,mn 40, kk, nn, mm JP.LIL cc,Mmn 5B, kk, nn, mm, MM Condition Relevant Flag Opcode (hex) NZ (non 0)
  • Page 191 ® eZ80 User Manual JP (HL) Jump Indirect Operation PC ← HL Description The Program Counter is loaded with the contents of the multibyte CPU register HL. Table 59 provides more detailed information on this instruction, particularly when switch- ing between ADL and Z80 modes.
  • Page 192 ® eZ80 User Manual JP (IX/Y) Jump Indirect Operation PC ← IX/Y Description The Program Counter is loaded with the contents of the specified Index Register, IX or IY. Table 60 provides more detailed information on this instruction, particularly when switch- ing between ADL and Z80 modes.
  • Page 193 ® eZ80 User Manual Mnemonic Operand ADL Mode Cycle Opcode (hex) (IY) JP.S 40, FD, E9 (IY) JP.L 5B, FD, E9 UM007714-0908 CPU Instruction Set...
  • Page 194 ® eZ80 User Manual JP Mmn Jump Operation PC ← Mmn Description The Program Counter is loaded with the instruction operand. When assembled, the first byte after the opcode is the low-order byte of the operand. Table 61 provides more detailed information on this instruction, particularly when switching between ADL and Z80 modes.
  • Page 195 ® eZ80 User Manual Mnemonic Operand ADL Mode Cycle Opcode (hex) JP.SIS 40, C3, nn, mm JP.LIL 5B, C3, nn, mm, MM UM007714-0908 CPU Instruction Set...
  • Page 196 ® eZ80 User Manual JR cc’, d Conditional Jump Relative Operation if cc’ { PC ← PC+d Description If the condition cc’ (NZ, Z, NC or C) is true (a logical 1), then the two’s-complement dis- placement d is added to the Program Counter. The jump is measured from the address of the byte following the instruction.
  • Page 197 ® eZ80 User Manual JR d Jump Relative Operation PC ← PC+d Description The two’s-complement displacement d is added to the Program Counter. The jump is mea- sured from the address of the byte following the instruction. Condition Bits Affected None.
  • Page 198 ® eZ80 User Manual LD A, I Load Accumulator Operation A ← I[7:0] Description The CPU writes the contents of the lower byte of the Interrupt Vector register, I[7:0], to the accumulator, A. Condition Bits Affected Set if the I register is negative; reset otherwise.
  • Page 199 ® eZ80 User Manual LD A, (IX/Y+d) Load Accumulator Operation A ← (IX/Y+d) Description The CPU writes the contents of the memory location specified by the contents of the IX or IY register offset by the two’s-complement displacement, d, to the accumulator, A.
  • Page 200 ® eZ80 User Manual LD A, MB Load Accumulator Operation A ← MBASE Description The CPU writes the contents of the Memory Base register, MBASE, to the accumulator, A. In Z80 mode, no operation occurs (two-cycle NOP). Condition Bits Affected None.
  • Page 201 40, 3A, nn, mm Note: Zilog recommends against using the .SIL and .LIS suffixes with this instruction. The .SIL instruction fetches a 24-bit value, Mmn. However, this instruction ignores the upper byte and uses address {MBASE, mm, nn} instead. The .LIS instruction fetches a 16-bit value, mn.
  • Page 202 ® eZ80 User Manual LD A, R Load Accumulator Operation A ← R Description The CPU writes the contents of the Refresh Counter register, R, to the accumulator, A. Condition Bits Affected Set if the R register is negative; reset otherwise.
  • Page 203 ® eZ80 User Manual LD A, (rr) Load Accumulator Operation A ← (rr) Description The rr operand is any of BC, DE, or HL. The CPU writes the contents of the memory location specified by the multibyte register to the accumulator, A.
  • Page 204 ® eZ80 User Manual LD HL, I Load Register Operation HL ← I Description The CPU writes the contents of the 16-bit Interrupt Vector register, I, to the multibyte reg- ister, HL. Condition Bits Affected Set if the I register is negative; reset otherwise.
  • Page 205 ® eZ80 User Manual LD (HL), IX/Y Load Indirect Operation (HL) ← IX/Y Description The CPU writes the contents of the multibyte Index Register IX or IY to the memory loca- tion specified by the contents of the multibyte HL register.
  • Page 206 ® eZ80 User Manual LD (HL), n Load Indirect Operation (HL) ← n Description The 8-bit immediate n operand is written to the memory location specified by the contents of the multibyte CPU register HL. Condition Bits Affected None. Attributes...
  • Page 207 ® eZ80 User Manual LD (HL), r Load Indirect Operation (HL) ← r Description The r operand is any of A, B, C, D, E, H, L. The CPU stores the contents of the specified register into the memory location specified by the contents of the multibyte HL register.
  • Page 208 ® eZ80 User Manual LD (HL), rr Load Indirect Operation (HL) ← rr Description The rr operand is any of the multibyte registers BC, DE, or HL. The CPU writes the con- tents of the multibyte register rr to the memory location specified by the contents of the multibyte HL register.
  • Page 209 ® eZ80 User Manual LD I, HL Load Interrupt Vector Operation I ← HL Description The CPU writes the contents of the accumulator, HL, to the 16-bit Interrupt Vector regis- ter, I. Condition Bits Affected None. Attributes Mnemonic Operand ADL Mode Cycle Opcode (hex)
  • Page 210 ® eZ80 User Manual LD I, A Load Interrupt Vector Operation I[7:0] ← A Description The CPU writes the contents of the accumulator, A, to the lower byte of the Interrupt Vec- tor register, I[7:0]. Condition Bits Affected None. Attributes...
  • Page 211 ® eZ80 User Manual LD ir, ir’ Load Operation ir ← ir’ Description The ir and ir’ operands are any of the 8-bit CPU registers IXH, IXL, IYH, or IYL. The CPU writes the contents of the specified register ir’ to the selected register ir.
  • Page 212 ® eZ80 User Manual LD ir, n Load Operation ir ← n Description The ir operand is any of the 8-bit CPU registers IXH, IXL, IYH, or IYL. The 8-bit imme- diate value n is written to the specified register ir.
  • Page 213 ® eZ80 User Manual LD ir, r Load Operation ir ← r Description The ir operand is any of the 8-bit CPU registers IXH, IXL, IYH, or IYL. The r operand is any of the 8-bit CPU registers A, B, C, D, or E. The CPU writes the contents of the speci- fied register r to the selected register ir.
  • Page 214 ® eZ80 User Manual Table 64. Register and jj Opcodes for LD ir, r Instruction (hex) Register jj identifies the A, B, C, D, or E register and is assembled into one of the opcodes indi- cated in Table Table 65. Register and kk Opcodes for LD ir, r Instruction (hex)
  • Page 215 ® eZ80 User Manual LD IX/Y, (HL) Load Index Register Operation IX/Y ← (HL) Description The CPU writes the contents of the memory location specified by the HL register to the multibyte Index Register, IX or IY. Condition Bits Affected None.
  • Page 216 ® eZ80 User Manual LD IX/Y, (IX/Y+d) Load Index Register Operation IX/Y ← (IX/Y+d) Description The CPU writes the contents of the memory location, specified by the contents of the IX or IY register offset by the two’s-complement displacement d, to the multibyte Index Reg- ister, IX or IY.
  • Page 217 ® eZ80 User Manual LD IX/Y, Mmn Load Index Register Operation IX/Y ← Mmn Description The immediate operand, Mmn, is written to the specified multibyte Index Register, IX or Condition Bits Affected None. Attributes Mnemonic Operand Mode Cycle Opcode (hex)
  • Page 218 40, FD, 2A, nn, mm Note: Zilog recommends against using the .SIL and .LIS suffixes with this instruction. The .SIL instruction fetches a 24-bit value, Mmn. However, this instruction ignores the upper byte and uses address {MBASE, mm, nn} instead. The .LIS instruction fetches a 16-bit value, mn.
  • Page 219 ® eZ80 User Manual LD (IX/Y+d), IX/Y Load Indirect with Offset Operation (IX/Y+d) ← IX/Y Description The CPU writes the contents of the Index Register, IX or IY, to the memory location spec- ified by the contents of the multibyte Index Register, IX or IY, offset by the two’s-comple- ment displacement d.
  • Page 220 ® eZ80 User Manual LD (IX/Y+d), n Load Indirect with Offset Operation (IX/Y+d) ← n Description The 8-bit immediate value n is written to the memory location specified by the contents of the multibyte Index Register, IX or IY, offset by the two’s-complement displacement d.
  • Page 221 ® eZ80 User Manual LD (IX/Y+d), r Load Indirect with Offset Operation (IX/Y+d) ← r Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The CPU writes the contents of the r register to the memory location specified by the contents of the multibyte Index Register, IX or IY, offset by the two’s-complement displacement d.
  • Page 222 ® eZ80 User Manual Table 66. Register and jj Opcodes for LD (IX/Y+d), r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 223 ® eZ80 User Manual LD (IX/Y+d), rr Load Indirect with Offset Operation (IX/Y+d) ← rr Description The rr operand is any of the multibyte registers BC, DE, or HL. The CPU writes the con- tents of the multibyte rr register to the memory location specified by the contents of the multibyte Index Register, IX or IY, offset by the two’s-complement displacement d.
  • Page 224 ® eZ80 User Manual LD MB, A Load MBASE Operation MBASE ← A Description In ADL mode (ADL mode bit = 1), the CPU writes the contents of the accumulator, A, to the MBASE register. otherwise., no operation occurs (two-cycle NOP).
  • Page 225 ® eZ80 User Manual LD (Mmn), A Load Indirect Operation (Mmn) ← A Description The CPU stores the contents of the accumulator, A, into the memory location specified by Mmn. Condition Bits Affected None. Attributes Mnemonic Operand ADL Mode Cycle Opcode (hex)
  • Page 226 5B, FD, 22, nn, mm, MM Note: Zilog recommends against using the .SIL and .LIS suffixes with this instruction. The .SIL instruction fetches a 24-bit value, Mmn. However, this instruction ignores the upper byte and uses address {MBASE, mm, nn} instead. The .LIS instruction fetches a 16-bit value, mn.
  • Page 227 5B, 22, nn, mm, MM Note: Zilog recommends against using the .SIL and .LIS suffixes with this instruction. The .SIL instruction fetches a 24-bit value, Mmn. However, this instruction ignores the upper byte and uses address {MBASE, mm, nn} instead. The .LIS instruction fetches a 16-bit value, mn.
  • Page 228 5B, ED, 73, nn, mm, MM Note: Zilog recommends against using the .SIL and .LIS suffixes with this instruction. The .SIL instruction fetches a 24-bit value, Mmn. However, this instruction ignores the upper byte and uses address {MBASE, mm, nn} instead. The .LIS instruction fetches a 16-bit value, mn.
  • Page 229 ® eZ80 User Manual LD R, A Load Refresh Counter Operation R ← A Description The CPU writes the contents of the accumulator, A, to the Refresh Counter register. Condition Bits Affected None. Attributes Mnemonic Operand ADL Mode Cycle Opcode (hex)
  • Page 230 ® eZ80 User Manual LD r, (HL) Load Register Operation r ← (HL) Description The r operand is any of A, B, C, D, E, H, or L. The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte CPU register HL. This 8-bit value is written to the specified r register.
  • Page 231 ® eZ80 User Manual LD r, ir Load Register Operation r ← ir Description The r operand is any of the 8-bit CPU registers A, B, C, D, or E. The ir operand is any of the 8-bit registers IXH, IXL, IYH, or IYL. The CPU writes the contents of the specified ir register to the selected r register.
  • Page 232 ® eZ80 User Manual Mnemonic Operand ADL Mode Cycle Opcode (hex) E,IYH FD, 5C E,IYL FD, 5D UM007714-0908 CPU Instruction Set...
  • Page 233 ® eZ80 User Manual LD r, (IX/Y+d) Load Register Operation r ← (IX/Y+d) Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The (IX/Y+d) oper- and is an 8-bit value at the memory location specified by the contents of the Index Regis- ter, IX or IY, added to the two’s-complement displacement d.
  • Page 234 ® eZ80 User Manual Table 68. Register and for LD r, (IX/Y+d) Instruction (hex) jj Opcodes Register jj UM007714-0908 CPU Instruction Set...
  • Page 235 ® eZ80 User Manual LD r, n Load Register Operation r ← n Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The 8-bit immedi- ate operand n is written to the specified r register.
  • Page 236 ® eZ80 User Manual LD r, r’ Load Register Operation r ← r’ Description The r and r’ operands are any of A, B, C, D, E, H, or L. The CPU writes the contents of the r’ register to the r register. The r’ register described here should not be confused with the registers in the alternate working register set.
  • Page 237 ® eZ80 User Manual LD rr, (HL) Load Register Operation rr ← (HL) Description The rr operand is any of the multibyte CPU registers BC, DE, or HL. The CPU writes the contents of the memory location specified by the HL register to the multibyte rr register.
  • Page 238 ® eZ80 User Manual LD rr, (IX/Y+d) Load Register Operation rr ← (IX/Y+d) Description The rr operand is any of the multibyte CPU registers BC, DE, or HL. The CPU writes the contents of the memory location, specified by the contents of the IX or IY register offset by the two’s-complement displacement d, to the multibyte rr register.
  • Page 239 ® eZ80 User Manual LD rr, Mmn Load Register Operation rr ← Mmn Description The rr operand is any of the multibyte CPU registers BC, DE, or HL. The immediate operand, Mmn, is written to the multibyte rr register. Condition Bits Affected None.
  • Page 240 Table Note: Zilog recommends against using the .SIL and .LIS suffixes with this instruction. The .SIL instruction fetches a 24-bit value, Mmn. However, this instruction ignores the upper byte and uses address {MBASE, mm, nn} instead. The .LIS instruction fetches a 16-bit value, mn.
  • Page 241 ® eZ80 User Manual Table 72. Register and kk Opcodes for LD rr, (Mmn) Instruction (hex) Register kk UM007714-0908 CPU Instruction Set...
  • Page 242 ® eZ80 User Manual LD (rr), A Load Indirect Operation (rr) ← A Description The rr operand is any of the multibyte registers BC, DE, or HL. The CPU stores the con- tents of the accumulator, A, in the memory location specified by the contents of the multi-...
  • Page 243 ® eZ80 User Manual LD SP, HL Load Stack Pointer Operation SP ← HL Description The CPU writes the contents of the multibyte CPU register HL to the Stack Pointer. In ADL mode, or when the .L suffix is employed, the destination is Stack Pointer Long (SPL).
  • Page 244 ® eZ80 User Manual LD SP, IX/Y Load Stack Pointer Operation SP ← IX/Y Description The CPU writes the contents of the specified multibyte Index Register, IX or IY, to the Stack Pointer. In ADL mode, or when the .L suffix is employed, the destination is Stack Pointer Long (SPL).
  • Page 245 ® eZ80 User Manual LD SP, Mmn Load Stack Pointer Operation SP ← Mmn Description The immediate operand, Mmn, is written to the multibyte Stack Pointer register (SP). In ADL mode, or when the .L suffix is employed, Stack Pointer Long (SPL) is the destina- tion.
  • Page 246 40, ED, 7B, nn, mm Note: Zilog recommends against using the .SIL and .LIS suffixes with this instruction. The .SIL instruction fetches a 24-bit value, Mmn. However, this instruction ignores the upper byte and uses address {MBASE, mm, nn} instead. The .LIS instruction fetches a 16-bit value, mn.
  • Page 247 ® eZ80 User Manual Load and Decrement Operation (DE) ← (HL) BC ← BC – 1 DE ← DE – 1 HL ← HL – 1 Description The CPU writes the contents of the memory location with an address contained in the mul- tibyte register HL to the memory location with the address contained in the multibyte reg- ister DE.
  • Page 248 ® eZ80 User Manual LDDR Load and Decrement with Repeat Operation repeat { (DE) ← (HL) BC ← BC – 1 DE ← DE – 1 HL ← HL – 1 } while (BC ≠ 0) Description The CPU writes the contents of the memory location with address contained in the multi- byte register HL to the memory location with address contained in the multibyte register DE.
  • Page 249 ® eZ80 User Manual Load and Increment Operation (DE) ← (HL) BC ← BC – 1 DE ← DE+1 HL ← HL+1 Description The CPU writes the contents of the memory location with address contained in the multi- byte register HL to the memory location with address contained in the multibyte register DE.
  • Page 250 ® eZ80 User Manual LDIR Load and Increment with Repeat Operation repeat { (DE) ← (HL) BC ← BC – 1 DE ← DE+1 HL ← HL+1 } while (BC ≠ 0) Description The CPU writes the contents of the memory location with the address contained in the multibyte register HL to the memory location with the address contained in the multibyte register DE.
  • Page 251 ® eZ80 User Manual LEA IX/Y, IX+d Load Effective Address Operation IX/Y ← IX+d Description The CPU adds the contents of the IX register to the signed displacement d and writes the sum to the specified multibyte Index Register, IX or IY.
  • Page 252 ® eZ80 User Manual LEA IX/Y, IY+d Load Effective Address Operation IX/Y ← IY+d Description The CPU adds the contents of the IY register to the two’s-complement displacement d and writes the sum to the specified multibyte Index Register, IX or IY.
  • Page 253 ® eZ80 User Manual LEA rr, IX+d Load Effective Address Operation rr ← IX+d Description The rr operand is any of the multibyte CPU registers BC, DE, or HL. The CPU adds the contents of the IX register to the signed displacement d and writes the sum to the multi- byte rr register.
  • Page 254 ® eZ80 User Manual LEA rr, IY+d Load Effective Address Operation rr ← IY+d Description The rr operand is any of the multibyte CPU registers BC, DE, or HL. The CPU adds the contents of the IY register to the signed displacement d and writes the sum to the multi- byte rr register.
  • Page 255 ® eZ80 User Manual MLT rr Multiply Register Operation rr[15:0] ← rr[15:8] x rr[7:0] Description The rr operand is any of the multibyte CPU registers BC, DE, or HL. The MLT instruc- tion performs an 8-bit by 8-bit multiply operation. The rr operand Low byte is multiplied by the rr operand High byte.
  • Page 256 ® eZ80 User Manual MLT SP Multiply Stack Pointer Operation SP[15:0] ← SP[15:8] x SP[7:0] Description The MLT SP instruction performs an 8-bit by 8-bit multiply operation using the Stack Pointer (SP). The SP Low byte is multiplied by the SP High byte. The 16-bit product is written back into the SP register.
  • Page 257 ® eZ80 User Manual Negate Accumulator Operation A ← 0 – A Description The contents of the accumulator, A, are negated (two’s-complemented) and are identical to a subtraction of the accumulator from 0. Condition Bits Affected Set if result is negative; reset otherwise.
  • Page 258 ® eZ80 User Manual No Operation Operation No operation. Description The CPU performs no operation during execution of this instruction. Condition Bits Affected None. Attributes Mnemonic Operand ADL Mode Cycle Opcode (hex) UM007714-0908 CPU Instruction Set...
  • Page 259 ® eZ80 User Manual OR A, (HL) Logical OR Operation A ← A OR (HL) Description The (HL) operand is the 8-bit value located at the memory location specified by the con- tents of the multibyte CPU register HL. This 8-bit value is logically ORed to the contents of the accumulator, A.
  • Page 260 ® eZ80 User Manual OR A, ir Logical OR Operation A ← A OR ir Description The rr operand is any of the 8-bit registers IXH, IXL, IYH, or IYL. The rr operand is log- ically ORed to the contents of the accumulator, A. The result is written to the accumulator.
  • Page 261 ® eZ80 User Manual OR A, (IX/Y+d) Logical OR Operation A ← A OR (IX/Y+d) Description The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d. This 8-bit value is logically ORed to the contents of the accumulator, A.
  • Page 262 ® eZ80 User Manual OR A, n Logical OR Operation A ← A OR n Description The 8-bit immediate value n is logically ORed to the contents of the accumulator, A. The result is written to the accumulator. Condition Bits Affected Set if result is negative;...
  • Page 263 ® eZ80 User Manual OR A, r Logical OR Operation A ← A OR r Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The r operand is logically ORed to the contents of the accumulator, A. The result is written to the accumu- lator.
  • Page 264 ® eZ80 User Manual Table 75. Register and Opcodes for OR A, r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 265 ® eZ80 User Manual OTD2R Output to I/O and Decrement with Repeat Operation repeat { ({UU, DE[15:0]}) ← (HL) BC ← BC – 1 DE ← DE – 1 HL ← HL – 1 } while BC ≠ 0 Description The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory.
  • Page 266 ® eZ80 User Manual C ← C – 1 HL ← HL – 1 } while B ≠ 0 UM007714-0908 CPU Instruction Set...
  • Page 267 ® eZ80 User Manual OTDM Output to I/O and Decrement Operation ({UU, 00h,C}) ← (HL) B ← B – 1 C ← C – 1 HL ← HL – 1 Description The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory.
  • Page 268 ® eZ80 User Manual OTDMR Output to I/O and Decrement Operation repeat { ({UU, 00h, C}) ← (HL) B ← B – 1 C ← C – 1 HL ← HL – 1 } while B ≠ 0 Description The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory.
  • Page 269 ® eZ80 User Manual OTDR Output to I/O and Decrement Operation repeat { ({UU, BC[15:0]}) ← (HL) B ← B – 1 HL ← HL – 1 } while B ≠ 0 Description The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory.
  • Page 270 ® eZ80 User Manual OTDRX Output to I/O and Decrement Memory Address with Stationary I/O Address Operation repeat { {UU, DE[15:0]} ← (HL) BC ← BC – 1 HL ← HL – 1 } while BC ≠ 0 Description The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory.
  • Page 271 ® eZ80 User Manual OTI2R Output to I/O and Increment with Repeat Operation repeat { ({UU, DE[15:0]}) ← (HL) BC ← BC – 1 DE ← DE+1 HL ← HL+1 } while BC ≠ 0 Description The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory.
  • Page 272 ® eZ80 User Manual repeat { ({UU, BC[15:0]}) ← (HL) B ← B – 1 C ← C+1 HL ← HL+1 } while B ≠ 0 UM007714-0908 CPU Instruction Set...
  • Page 273 ® eZ80 User Manual OTIM Output to I/O and Increment Operation ({UU, 00h,C}) ← (HL) B ← B – 1 C ← C+1 HL ← HL+1 Description The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory.
  • Page 274 ® eZ80 User Manual OTIMR Output to I/O and Increment Operation repeat { ({UU, 00h, C}) ← (HL) B ← B – 1 C ← C+1 HL ← HL+1 } while B ≠ 0 Description The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory.
  • Page 275 ® eZ80 User Manual OTIR Output to I/O and Increment Operation repeat { ({UU, BC[15:0]}) ← (HL) B ← B – 1 HL ← HL+1 } while B ≠ 0 Description The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory.
  • Page 276 ® eZ80 User Manual OTIRX Output to I/O and Increment Memory Address with Stationary I/O Address Operation repeat { {UU, DE[15:0]} ← (HL) BC ← BC – 1 HL ← HL+ 1 } while BC ≠ 0 Description The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory.
  • Page 277 ® eZ80 User Manual OUT (BC), r—also OUT (C), r for Z80 compatibility Output to I/O Operation ({UU, BC[15:0]}) ← r Description The r operand is any of the A, B, C, D, E, H, and L registers. The CPU outputs the con- tents of this byte of the specified register to the I/O address {UU, BC[15:0]}.
  • Page 278 ® eZ80 User Manual OUT (n), A Output to I/O Operation ({UU, A, n}) ← A Description The n operand is placed on the lower byte of the address bus, ADDR[7:0]. The CPU places the contents of the accumulator, A, onto the middle byte of the address bus, ADDR[15:8].
  • Page 279 ® eZ80 User Manual OUT0 (n), r Output to I/O Operation ({UU, 00h, n}) ← r Description The r operand is any of A, B, C, D, E, H, or L. The n operand is placed on the lower byte of the address bus, ADDR[7:0], while the High byte of the address bus, ADDR[15:8], is forced to 0.
  • Page 280 ® eZ80 User Manual OUTD Output to I/O and Decrement Operation ({UU, BC[15:0]}) ← (HL) B ← B – 1 HL ← HL – 1 Description The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory.
  • Page 281 ® eZ80 User Manual OUTD2 Output to I/O and Decrement Operation ({UU, BC[15:0]}) ← (HL) B ← B – 1 C ← C – 1 HL ← HL – 1 Description The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory.
  • Page 282 ® eZ80 User Manual OUTI Output to I/O and Increment Operation ({UU, BC[15:0]}) ← (HL) B ← B – 1 HL ← HL+1 Description The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. The CPU next outputs this byte to I/O address {UU, BC[15:0]}. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses.
  • Page 283 ® eZ80 User Manual OUTI2 Output to I/O and Increment Operation ({UU, BC[15:0]}) ← (HL) B ← B – 1 C ← C+1 HL ← HL+1 Description The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory.
  • Page 284 ® eZ80 User Manual PEA IX+d Push Effective Address Operation if ADL mode{ (SPL – 1) ← IXd[23:16] (SPL – 2) ← IXd[15:8] (SPL – 3) ← IXd[7:0] SPL ← SPL – 3 else Z80 mode { (SPS – 1) ← IXd[15:8] (SPS –...
  • Page 285 ® eZ80 User Manual PEA IY+d Push Effective Address Operation if ADL mode{ (SPL – 1) ← IYd[23:16] (SPL – 2) ← IYd[15:8] (SPL – 3) ← IYd[7:0] SPL ← SPL – 3 else Z80 mode { (SPS – 1) ← IYd[15:8] (SPS –...
  • Page 286 ® eZ80 User Manual POP AF Pop Stack Operation if ADL mode { F ← (SPL) A ← (SPL+1) Discard ← (SPL+2) SPL ← SPL+3 else Z80 mode { F ← (SPS) A ← (SPS+1) SPS ← SPS+2 Description In ADL mode, or when the .L suffix is employed, 3 bytes are popped off the stack begin- ning at the memory location specified by SPL.
  • Page 287 ® eZ80 User Manual POP IX/Y Pop Stack Operation if ADL mode { IX/Y[7:0] ← (SPL) IX/Y[15:8] ← (SPL+1) IX/Y[23:16] ← (SPL+2) SPL ← SPL+3 else Z80 mode { IX/Y[7:0] ← (SPS) IX/Y[15:8] ← (SPS+1) SPS ← SPS+2 Description In ADL mode, or when the .L suffix is employed, 3 bytes are popped off the stack begin- ning at the memory location specified by SPL.
  • Page 288 ® eZ80 User Manual Mnemonic Operand ADL Mode Cycle Opcode (hex) POP.S 52, FD, E1 POP.L 49, FD, E1 UM007714-0908 CPU Instruction Set...
  • Page 289 ® eZ80 User Manual POP rr Pop Stack Operation if ADL mode { rr[7:0]← (SPL) rr[15:8]← (SPL+1) rr[23:16]← (SPL+2) SPL ← SPL+3 else Z80 mode { rr[7:0]← (SPS) rr[15:8]← (SPS+1) SPS ← SPS+2 Description The rr operand is any of the multibyte CPU registers BC, DE, or HL.
  • Page 290 ® eZ80 User Manual identifies either the BC, DE, or HL multibyte register and is assembled into one of the opcodes indicated in Table Table 78. Register and kk Opcodes for POP rr Instruction (hex) Register kk UM007714-0908 CPU Instruction Set...
  • Page 291 ® eZ80 User Manual PUSH AF Push Stack Operation if ADL mode { (SPL – 1) ← 00h (SPL – 2) ← A (SPL – 3) ← F SPL ← SPL – 3 else Z80 mode { (SPS – 1) ← A (SPS –...
  • Page 292 ® eZ80 User Manual Attributes Mnemonic Operand ADL Mode Cycle Opcode (hex) PUSH PUSH.S 52, F5 PUSH.L 49, F5 UM007714-0908 CPU Instruction Set...
  • Page 293 ® eZ80 User Manual PUSH IX/Y Push Stack Operation if ADL mode { (SPL – 1) ← IX/Y[23:16] (SPL – 2) ← IX/Y[15:8] (SPL – 3) ← IX/Y[7:0] SPL ← SPL – 3 else Z80 mode { (SPS – 1) ← IX/Y[15:8] (SPS –...
  • Page 294 ® eZ80 User Manual Attributes Mnemonic Operand ADL Mode Cycle Opcode (hex) PUSH DD, E5 PUSH.S 52, DD, E5 PUSH.L 49, DD, E5 PUSH FD, E5 PUSH.S 52, FD, E5 PUSH.L 49, FD, E5 UM007714-0908 CPU Instruction Set...
  • Page 295 ® eZ80 User Manual PUSH rr Push Stack Operation if ADL mode { (SPL – 1) ← rr[23:16] (SPL – 2) ← rr[15:8] (SPL – 3) ← rr[7:0] SPL ← SPL – 3 else Z80 mode { (SPS – 1) ← rr[15:8] (SPS –...
  • Page 296 ® eZ80 User Manual Attributes Mnemonic Operand ADL Mode Cycle Opcode (hex) PUSH PUSH.S 52, kk PUSH.L 49, kk identifies either the BC, DE, or HL multibyte register and is assembled into one of the opcodes indicated in Table Table 79. Register and kk Opcodes for PUSH rr Instruction (hex)
  • Page 297 ® eZ80 User Manual RES b, (HL) Reset Bit Operation (HL)[b] ← 0 Description The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). Bit b of this value is reset to 0.
  • Page 298 ® eZ80 User Manual RES b, (IX/Y+d) Reset Bit Operation (IX/Y+d)[b] ← 0 Description The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d. Bit b of this value is reset to 0.
  • Page 299 ® eZ80 User Manual Table 81. Opcodes for RES b, (IX/Y+ ) Instruction (hex) Tested UM007714-0908 CPU Instruction Set...
  • Page 300 ® eZ80 User Manual RES b, r Reset Bit Operation r[b] ← 0 Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. Bit b of the speci- fied register r is reset to 0.
  • Page 301 ® eZ80 User Manual Return from Subroutine Operation PC ← (SP) Description The RET instruction returns program control back to the point in the user’s application code that had reached the current subroutine via a CALL instruction. The return address pops from the stack and is written to the Program Counter.
  • Page 302 ® eZ80 User Manual Table 83. RET Instruction Detail (Continued) Suffix Operation The starting Program Counter is {MBASE, PC[15:0]}. Pop a byte from SPL into ADL to set memory mode (03h = ADL, 02h = Z80). if ADL mode { Pop the upper byte of the return address from SPL into PC[23:16].
  • Page 303 ® eZ80 User Manual RET cc Conditional Return from Subroutine Operation if cc { PC ← (SP) Description If the condition is true (1), the RET instruction returns program control back to the point in the user’s application code that had reached the current subroutine via a CALL instruc- tion.
  • Page 304 ® eZ80 User Manual Table 84. RET cc Instruction Detail (Continued) The starting Program Counter is {MBASE, PC[15:0]}. Pop a byte from SPL into ADL to set the new memory mode (03h = ADL, 02h = Z80). if ADL mode { Pop the upper byte of the return address from SPL into PC[23:16].
  • Page 305 ® eZ80 User Manual Mnemonic Operand Mode Cycle Opcode (hex) 3 if cc false, RET.L 49, kk 8 if cc true and return to Z80 Mode, 9 if cc true and return to ADL Mode 3 if cc false, RET.L...
  • Page 306 ® eZ80 User Manual RETI Return from Maskable Interrupt Operation PC ← (SP) Description The RETI instruction returns program control back to the point in the user’s application code where an interrupt caused the program control to jump to the current maskable inter- rupt service routine.
  • Page 307 ® eZ80 User Manual Table 86. RET Instruction Detail Suffix Operation The MADL control bit must be set to 1 to enable mixed- ADL mode interrupts. The starting Program Counter is {MBASE, PC[15:0]}. Pop a byte from SPL into ADL to set the new memory mode (03h = ADL, 02h = Z80).
  • Page 308 ® eZ80 User Manual Mnemonic Operand Mode Cycle Opcode (hex) — 8 if return to Z80 RETI.L 49, ED, 4D Mode, 9 if return to ADL Mode — 8 if return to Z80 RETI.L 5B, ED, 4D Mode, 9 if return to ADL...
  • Page 309 ® eZ80 User Manual RETN Return from Nonmaskable Interrupt Operation PC ← (SP) IEF1 ← IEF2 Description The RETN instruction returns program control back to the point in the user’s application code where an interrupt caused the program control to jump to the current nonmaskable interrupt service routine.
  • Page 310 ® eZ80 User Manual Table 87. RETN Instruction Detail (Continued) Suffix Operation The MADL control bit must be set to 1 to enable mixed- ADL mode interrupts. The starting Program Counter is {MBASE, PC[15:0]}. Pop a byte from SPL into ADL to set the new memory mode (03h = ADL, 02h = Z80).
  • Page 311 ® eZ80 User Manual Attributes Mnemonic Operand Mode Cycle Opcode (hex) — RETN ED, 45 — 8 if return to Z80 RETN.L 49, ED, 45 Mode, 9 if return to ADL Mode — 8 if return to Z80 RETN.L 5B, ED, 45...
  • Page 312 ® eZ80 User Manual RL (HL) Rotate Left Operation (HL) Description The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). The CPU manipulates the contents of this memory location, (HL), by rotating them left one bit position.
  • Page 313 ® eZ80 User Manual RL (IX/Y+d) Rotate Left Operation (IX/Y+d) Description The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d. The CPU manipulates the contents of this memory location, (IX/Y+d), by rotating them left one bit position.
  • Page 314 ® eZ80 User Manual RL r Rotate Left Operation Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The CPU manipu- lates the contents of the r operand by rotating them left one bit position. The CPU next copies bit 7 into the Carry Flag and copies the previous contents of the Carry Flag into bit 0 of the r operand.
  • Page 315 ® eZ80 User Manual Table 88. Register and Opcodes for RL r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 316 ® eZ80 User Manual Rotate Left Accumulator Operation Description The CPU manipulates the contents of the accumulator, A, by rotating them left one bit position. The CPU next copies bit 7 into the Carry Flag and copies the previous contents of the Carry Flag into bit 0 of the m operand.
  • Page 317 ® eZ80 User Manual RLC (HL) Rotate Left with Carry Operation (HL) Description The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). The CPU manipulates the contents of this memory location, (HL), by rotating them left one bit position.
  • Page 318 ® eZ80 User Manual RLC (IX/Y+d) Rotate Left with Carry Operation (IX/Y+d) Description The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d. The CPU manipulates the contents of this memory location, (IX/Y+d), by rotating them left one bit position.
  • Page 319 ® eZ80 User Manual RLC r Rotate Left with Carry Operation Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The CPU manipu- lates the contents of the r operand by rotating them left one bit position. The CPU next copies bit 7 into the Carry Flag and into bit 0 of the r operand.
  • Page 320 ® eZ80 User Manual Table 89. Register and Opcodes for RLC r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 321 ® eZ80 User Manual RLCA Rotate Left with Carry–Accumulator Operation Description The CPU manipulates the contents of the accumulator, A, by rotating them left one bit position. The CPU next copies bit 7 into the Carry Flag and into bit 0.
  • Page 322 ® eZ80 User Manual Rotate Left Decimal Operation (HL) A[3:0] ← HL[7:4] HL[7:4] ← HL[3:0] HL[3:0] ← A[3:0] Description The CPU copies the contents of the low-order four bits of the memory location (HL) into the high-order four bits of the (HL). The CPU next copies the previous contents of the high-order four bits of the (HL) into the low-order four bits of the accumulator, A.
  • Page 323 ® eZ80 User Manual RR (HL) Rotate Right Operation (HL) Description The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). The CPU manipulates the contents of this memory location, (HL), by rotating them right one bit position.
  • Page 324 ® eZ80 User Manual RR (IX/Y+d) Rotate Right Operation (IX/Y+d) Description The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d. The CPU manipulates the contents of this memory location, (IX/Y+d), by rotating them right one bit position.
  • Page 325 ® eZ80 User Manual RR r Rotate Right Operation Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The CPU manipu- lates the contents of the r operand by rotating them right one bit position. The CPU next copies the contents of bit 0 into the Carry Flag and copies the previous contents of the Carry Flag into bit 7 of the r operand.
  • Page 326 ® eZ80 User Manual Table 90. Register and Opcodes for RR r Instruction (hex) (Continued) Register jj UM007714-0908 CPU Instruction Set...
  • Page 327 ® eZ80 User Manual Rotate Right–Accumulator Operation Description The CPU manipulates the contents of the accumulator, A, by rotating them right one bit position. The CPU next copies the contents of bit 0 into the Carry Flag and copies the pre- vious contents of the Carry Flag into bit 7.
  • Page 328 ® eZ80 User Manual RRC (HL) Rotate Right with Carry Operation (HL) Description The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). The CPU manipulates the contents of this memory location, (HL), by rotating them right one bit position.
  • Page 329 ® eZ80 User Manual RRC (IX/Y+d) Rotate Right with Carry Operation (IX/Y+d) Description The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d. The CPU manipulates the contents of this memory location, (IX/Y+d), by rotating them right one bit position.
  • Page 330 ® eZ80 User Manual RRC r Rotate Right with Carry Operation Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The CPU manipu- lates the contents of the r operand by rotating them right one bit position. The CPU next copies the contents of bit 0 into the Carry Flag and into bit 7 of the r operand.
  • Page 331 ® eZ80 User Manual Table 91. Register and Opcodes for RRC r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 332 ® eZ80 User Manual RRCA Rotate Right with Carry–Accumulator Operation Description The CPU manipulates the contents of the accumulator, A, by rotating them right one bit position. The CPU next copies the contents of bit 0 into the Carry Flag and into bit 7.
  • Page 333 ® eZ80 User Manual Rotate Right Decimal Operation (HL) A[3:0] ← HL[3:0] HL[7:4] ← A[3:0] HL[3:0] ← HL[7:4] Description The CPU copies the contents of the low-order four bits of the memory location (HL) into the low-order four bits of the accumulator, A. The CPU next copies the previous contents of the low-order four bits of the accumulator into the high-order four bits of (HL).
  • Page 334 ® eZ80 User Manual RSMIX Reset MIXED MEMORY Mode Flag Operation MADL ← 0 Description The MIXED MEMORY Mode Flag (MADL) is reset to 0. Condition Bits Affected None. Attributes Mnemonic Operand ADL Mode Cycle Opcode (hex) — RSMIX ED, 7E...
  • Page 335 ® eZ80 User Manual RST n Restart Operation (SP) ← PC PC ← {0000h,n} Description The RST instruction functions similar to a CALL instruction. However, the 8-bit n oper- and is limited to 8 specific values: , and . After stacking the Program Counter (and ADL mode bit, if necessary), the RST instruction is written the 8-bit restart vector n to the Program Counter.
  • Page 336 ® eZ80 User Manual Table 92. RST N Instruction Detail The starting Program Counter is {MBASE, PC[15:0]}. Push the 2-byte return address, PC[15:0], onto the SPL stack. Push a 02h byte onto the SPL stack, indicating an interrupt from Z80 mode, because ADL = 0. Set the ADL mode bit to 1.
  • Page 337 ® eZ80 User Manual Table 93. Restart Address and kk Opcodes for RST n Instruction (hex) (Continued) Restart Address UM007714-0908 CPU Instruction Set...
  • Page 338 ® eZ80 User Manual SBC A, (HL) Subtract with Carry Operation A ← A–(HL)–C Description The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). This 8-bit value and the Carry Flag (C) are subtracted from the contents of the accumulator, A.
  • Page 339 ® eZ80 User Manual SBC A, ir Subtract with Carry Operation A ← A – ir – C Description The rr operand is any of the 8-bit registers IXH, IXL, IYH, IYL. The ir operand and the Carry Flag (C) are subtracted from the contents of the accumulator, A. The result is writ- ten to the accumulator.
  • Page 340 ® eZ80 User Manual SBC A, (IX/Y+d) Subtract with Carry Operation A ← A–(IX/Y+d)–C Description The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d. This 8-bit value and the Carry Flag (C) are subtracted from the contents of the accumulator, A.
  • Page 341 ® eZ80 User Manual SBC A, n Subtract with Carry Operation A ← A – n – C Description The 8-bit immediate value n and the Carry Flag (C) are subtracted from the contents of the accumulator, A. The result is written to the accumulator.
  • Page 342 ® eZ80 User Manual SBC A, r Subtract with Carry Operation A ← A – r – C Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The r operand and the Carry Flag (C) are subtracted from the contents of the accumulator, A.
  • Page 343 ® eZ80 User Manual Table 94. Register and Opcodes for SBC A, r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 344 ® eZ80 User Manual SBC HL, rr Subtract with Carry Operation HL ← HL – rr – C Description The rr operand is any of the multibyte CPU registers BC, DE, or HL. The rr operand and the Carry Flag (C) are subtracted from the contents of the HL register. The result is written to HL.
  • Page 345 ® eZ80 User Manual Table 95. Register and Opcodes for SBC HL, rr Instruction (hex) Register kk UM007714-0908 CPU Instruction Set...
  • Page 346 ® eZ80 User Manual SBC HL, SP Subtract with Carry Operation HL ← HL – SP – C Description The Stack Pointer (SP) and the Carry Flag (C) are subtracted from the contents of the HL register. The result is written to HL. In ADL mode, or if the .L suffix is employed, the 24- bit Stack Pointer Long (SPL) is used.
  • Page 347 ® eZ80 User Manual Set Carry Flag Operation C ← 1 Description The Carry Flag, C, is set to 1. Condition Bits Affected Not affected. Not affected. Reset. Not affected. Reset. Set. Attributes Mnemonic Operand ADL Mode Cycle Opcode (hex) —...
  • Page 348 ® eZ80 User Manual SET b, (HL) Set Bit Operation (HL)[b] ← 1 Description The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). Bit b of this 8-bit value is set to 1.
  • Page 349 ® eZ80 User Manual SET b, (IX/Y+d) Set Bit Operation (IX/Y+d)[b] ← 1 Description The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d. Bit b this 8-bit value is set to 1.
  • Page 350 ® eZ80 User Manual Table 97. Opcodes for SET b, (IX/Y+d) Instruction (hex) Tested UM007714-0908 CPU Instruction Set...
  • Page 351 ® eZ80 User Manual SET b, r Set Bit Operation r[b] ← 1 Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. Bit b of the speci- fied register is set to 1.
  • Page 352 ® eZ80 User Manual SLA (HL) Shift Left Arithmetic Operation (HL) Description The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). The CPU manipulates the contents of this memory location, (HL), by shifting them left one bit position.
  • Page 353 ® eZ80 User Manual SLA (IX/Y+d) Shift Left Arithmetic Operation (IX/Y+d) Description The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d. The CPU manipulates the contents of this memory location, (IX/Y+d), by shifting them left one bit position.
  • Page 354 ® eZ80 User Manual SLA r Shift Left Arithmetic Operation Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The CPU manipu- lates the contents of the r operand by shifting them left one bit position. The CPU next copies bit 7 into the Carry Flag and copies a 0 into bit 0 of the r operand.
  • Page 355 ® eZ80 User Manual Table 99. Register and Opcodes for SLA r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 356 User Manual Sleep Operation This instruction places the CPU into SLEEP mode. Description ® SLEEP mode may not be supported on some eZ80 devices. Refer to the individual prod- uct specification for a detailed description. Condition Bits Affected None. Attributes...
  • Page 357 ® eZ80 User Manual SRA (HL) Shift Right Arithmetic Operation (HL) Description The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). The CPU manipulates the contents of this memory location, (HL), by shifting them right one bit position.
  • Page 358 ® eZ80 User Manual SRA (IX/Y+d) Shift Right Arithmetic Operation (IX/Y+d) Description The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d. The CPU manipulates the contents of this memory location, (IX/Y+d), by shifting them right one bit position.
  • Page 359 ® eZ80 User Manual SRA r Shift Right Arithmetic Operation Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The CPU manipu- lates the contents of the r operand by shifting them right one bit position. The CPU next copies the contents of bit 0 into the Carry Flag and leaves the previous contents of bit 7 unchanged.
  • Page 360 ® eZ80 User Manual Table 100. Register and Opcodes for SRA r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 361 ® eZ80 User Manual SRL (HL) Shift Right Logical Operation (HL) Description The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). The CPU manipulates the contents of this memory location, (HL), by shifting them right one bit position.
  • Page 362 ® eZ80 User Manual SRL (IX/Y+d) Shift Right Logical Operation (IX/Y+d) Description The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d. The CPU manipulates the contents of this memory location, (IX/Y+d), by shifting them right one bit position.
  • Page 363 ® eZ80 User Manual SRL r Shift Right Logical Operation Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The CPU manipu- lates the contents of the r operand by shifting them right one bit position. The CPU next copies the contents of bit 0 into the Carry Flag and resets bit 7.
  • Page 364 ® eZ80 User Manual Table 101. Register and Opcodes for SRL r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 365 ® eZ80 User Manual STMIX Set MIXED MEMORY Mode Flag Operation MADL ← 1 Description The MIXED MEMORY Mode Flag (MADL) is set to 1. Condition Bits Affected None. Attributes Mnemonic Operand ADL Mode Cycle Opcode (hex) STMIX — ED, 7D...
  • Page 366 ® eZ80 User Manual SUB A, (HL) Subtract without Carry Operation A ← A–(HL) Description The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). This 8-bit value is subtracted from the contents of the accumula- tor, A.
  • Page 367 ® eZ80 User Manual SUB A, ir Subtract without Carry Operation A ← A – ir Description The ir operand is any of the 8-bit registers IXH, IXL, IYH, or IYL. The ir operand is sub- tracted from the contents of the accumulator, A. The result is written to the accumulator.
  • Page 368 ® eZ80 User Manual SUB A, (IX/Y+d) Subtract without Carry Operation A ← A – (IX/Y + d) Description The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d. This 8-bit value is subtracted from the contents of the accumulator, A.
  • Page 369 ® eZ80 User Manual SUB A, n Subtract without Carry Operation A ← A – n Description The 8-bit immediate value n is subtracted from the contents of the accumulator, A. The result is written to the accumulator. Condition Bits Affected Set if result is negative;...
  • Page 370 ® eZ80 User Manual SUB A, r Subtract without Carry Operation A ← A – r Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The r operand is subtracted from the contents of the accumulator, A. The result is written to the accumula- tor.
  • Page 371 ® eZ80 User Manual Table 102. Register and Opcodes for SUB A, r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 372 ® eZ80 User Manual TST A, (HL) Test Operation A AND (HL) Description The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). This 8-bit value is bitwise ANDed with the contents of the accu- mulator, A.
  • Page 373 ® eZ80 User Manual TST A, n Test Operation A AND n Description The 8-bit immediate value n is bitwise ANDed with the contents of the accumulator, A. The appropriate flags are set to 1, depending on the result of the AND logical operation.
  • Page 374 ® eZ80 User Manual TST A, r Test Operation A AND r Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The r operand is bitwise ANDed with the contents of the accumulator, A. The appropriate flags are set to 1, depending on the result of the AND logical operation.
  • Page 375 ® eZ80 User Manual Table 103. Register and Opcodes for TST A, r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 376 ® eZ80 User Manual TSTIO n Test I/O Byte Operation {0000h, C} AND n Description The CPU places the contents of the C register onto the lower byte of the address bus, ADDR[7:0], while it forces the two upper bytes of the address bus, ADDR[23:0], to 0s.
  • Page 377 ® eZ80 User Manual XOR A, (HL) Logical Exclusive OR Operation A ← A XOR (HL) Description The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). This 8-bit value is bitwise exclusive-ORed with the contents of the accumulator, A.
  • Page 378 ® eZ80 User Manual XOR A, ir Logical Exclusive OR Operation A ← A XOR ir Description The ir operand is any of the 8-bit registers IXH, IXL, IYH, or IYL. The ir operand is bit- wise exclusive-ORed with the contents of the accumulator, A. The result is written to the accumulator.
  • Page 379 ® eZ80 User Manual XOR A, (IX/Y+d) Logical Exclusive OR Operation A ← A XOR (IX/Y+d) Description The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-complement displacement d. This 8-bit value is bitwise exclusive-ORed with the contents of the accumulator, A.
  • Page 380 ® eZ80 User Manual Table 104. Register and Opcodes for XOR A, (IX/Y+d) Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...
  • Page 381 ® eZ80 User Manual XOR A, n Logical Exclusive OR Operation A ← A XOR n Description The 8-bit immediate value n is bitwise exclusive-ORed with the contents of the accumula- tor, A. The result is written to the accumulator.
  • Page 382 ® eZ80 User Manual XOR A, r Logical Exclusive OR Operation A ← A XOR r Description The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The r operand is bitwise exclusive-ORed with the contents of the accumulator, A. The result is written to the accumulator.
  • Page 383 ® eZ80 User Manual Table 105. Register and Opcodes for XOR A, r Instruction (hex) Register jj UM007714-0908 CPU Instruction Set...

  • Page 384: Opcode Maps

    ® eZ80 User Manual Opcode Maps Table 106. Opcode Map—First Opcode Lower Opcode Nibble Legend Upper Opcode Nibble Mnemonic First Operand Second Operand Lower Nibble (Hex) RLCA RRCA (BC),A AF,AF’ HL,BC A,(BC) DJNZ (DE),A HL,DE A,(DE) (Mmn), NZ,d HL,HL (Mmn)
  • Page 385 ® eZ80 User Manual Table 107. Opcode Map—Second Opcode after 0CBh Legend Lower Nibble of 2nd Opcode Upper Nibble of Second Mnemonic Opcode First Operand Second Operand Lower Nibble (Hex) (HL) (HL) (HL) (HL) (HL) (HL) (HL) 0,(HL) 1,(HL) 2,(HL)
  • Page 386 ® eZ80 User Manual Table 108. Opcode Map—Second Opcode After 0DDh Legend Lower Nibble of 2nd Opcode Upper Nibble of Second Mnemonic Opcode SP,IX First Operand Second Operand Lower Nibble (Hex) LD BC, (IX+d), (IX+d) IX,BC LD DE, (IX+d), (IX+d)
  • Page 387 ® eZ80 User Manual Table 109. Opcode Map—Second Opcode After 0EDh Legend Lower Nibble of 2nd Opcode Upper Nibble of Second Mnemonic Opcode HL,BC First Operand Second Operand Lower Nibble (Hex) OUT0 LEA BC LEA BC LD BC, OUT0 LD (HL),...
  • Page 388 ® eZ80 User Manual Table 110. Opcode Map—Second Opcode After 0FDh Legend Lower Nibble of 2nd opcode Upper Nibble of Second Mnemonic opcode SP,IY First Operand Second Operand Lower Nibble (Hex) LD BC, LD (IY (IY+d) IY,BC +d),BC LD DE,...
  • Page 389 ® eZ80 User Manual Table 111. Opcode Map—Fourth Byte After , and 0DDh 0CBh Legend Lower Nibble of 4th Byte Upper Nibble of Fourth Mnemonic Byte 0,(IX+d) First Operand Second Operand Lower Nibble (Hex) (IX+d) (IX+d) (IX+d) (IX+d) (IX+d) (IX+d)
  • Page 390 ® eZ80 User Manual Table 112. Opcode Map—Fourth Byte After , and 0FDh 0CBh Legend Lower Nibble of 4th Byte Upper Nibble of Fourth Mnemonic Byte 0,(IY+d) First Operand Second Operand Lower Nibble (Hex) (IY+d) (IY+d) (IY+d) (IY+d) (IY+d) (IY+d)

  • Page 391: Glossary

    ROM to store code, and RAM for data. The memory can also be divided logically to form separate areas for code and data storage. ® ADDRESS AND DATA LONG mode takes advantage of the eZ80 CPU’s 16 MB linear addressing ADL.
  • Page 392 ® eZ80 User Manual Arithmetic Logical Unit (ALU). the element that can perform the basic data manipulations in the central processor. Usually, the ALU can add, subtract, complement, negate, rotate, AND, and OR. array. An arrangement of elements in one or more dimensions. In a programming language, an aggregate that consists of data objects with identical attributes, each of which may be uniquely referenced by subscription.
  • Page 393 ® eZ80 User Manual Bit Error Ratio Tester (BERT). A testing device that compares a received data pattern with a known transmitted pattern to determine the level of transmission quality. bit configuration. The sequence of bits used to encode a character.
  • Page 394 Dual-Channel Asynchronous Receiver/Transmitter—an SIO that supports asynchronous data communications only. ® data bus. An I/O bus used by the eZ80 CPU for passing data to and from internal and external memory. DCE. Data Circuit-terminating Equipment—connects data terminal equipment (DTE) to a data circuit. A modem is an example of a DCE.
  • Page 395 Zilog’s next-generation Internet processor core. A single-cycle instruction fetch machine that is eZ80 four times faster than Zilog’s original Z80, offering linear addressing that can address up to 16 MB of memory. The act of retrieving information (instructions or data) from memory.
  • Page 396 The three types of interrupts include: internal hardware, external hardware, and software. ® The time required for the eZ80 CPU to respond to an interrupt service interrupt acknowledge cycle.
  • Page 397 8-bit accumulator register (A) and six 8-bit working registers (B, C, D, E, H, and L). See Alternate register set. ® Maskable interrupts can be enabled and disabled. If enabled, the eZ80 CPU will Maskable Interrupt. respond to a maskable interrupt service request from an external device or on-chip peripheral. If disabled, ®...
  • Page 398 Nonmaskable interrupt. NMI. ® Nonmaskable interrupts are always enabled. The eZ80 CPU will always Nonmaskable Interrupt. respond to a nonmaskable interrupt service request from an external device or on-chip peripheral. A nonmaskable interrupt cannot be disabled by the programmer.
  • Page 399 PEA. Push Effective Address; a load instruction. ® Persistent mode. One of two types of mode changes available to the eZ80 . Persistent mode switches ® allow the eZ80 to operate for long periods in ADL mode, then switch to Z80 mode to run a section of Z80 code, and then return to ADL mode.
  • Page 400 The Sign flag stores the state of the most significant bit of the accumulator (bit 7). ® tion mode. One of two types of mode changes available to the eZ80 . Single-instruction mode changes allow certain instructions to operate using either ADL or Z80 addressing mode without making a persistent change to either mode.
  • Page 401 Two are normal low-impedance 1 and 0 states; the third is a high-impedance state that allows many tristate devices to time-share bus lines. This industry term is not trademarked, and is available for Zilog use. Do not use 3-state or three-state. Test Accumulator; a logical instruction.
  • Page 402 See X XTAL2. ZDS. Zilog Developer Studio. Zilog’s program development environment for Windows 95/98/NT. Zero Flag. For 8-bit arithmetic and logical operations, the Z Flag is set to 1 if the resulting byte in the accumulator is 0. If the byte is not 0, the Z Flag is reset to 0.

  • Page 403: Index

    ® eZ80 User Manual Index Numerics ADL Mode 13 ADL mode 2, 3, 6, 7, 8, 10, 12, 18, 20, 25, 26, 28, 16-MB address mode 1 31, 32, 33, 34, 35, 37, 38, 40, 41, 46, 48, 67, 72...
  • Page 404 EXX 147 Customer Support 402 EXX instruction 48 cycle time 3 eZ80 1, 2, 20, 21, 34, 36, 37, 38, 48 eZ80 CPU Response to a Maskable Interrupt 38 eZ80 CPU Response to a Nonmaskable Interrupt 37 DAA 129 eZ80 MEMORY mode prefix bytes 25...
  • Page 405 ® eZ80 User Manual INDMR 168 INDR 169 f 33, 39, 247, 282 INDRX 170 full 24-bit address mode 1 INI 171 INI2 172 INI2R 173 Half-Carry Flag 17, 386 INIM 175 HALT 148 INIMR 176 Halt 148 INIR 177...
  • Page 406 ® eZ80 User Manual JP (HL) 182 LD IX/Y, Mmn 208 JP (IX/Y) 183 LD MB, A 215 JP cc, Mmn 180 LD r, (HL) 221 JP Mmn 185 LD r, (IX/Y + d) 224 JR cc’, d 187 LD R, A 220...
  • Page 407 ® eZ80 User Manual Load Register 221, 222, 224, 226, 227, 228, 229, NOP 249 230, 231 Load Stack Pointer 234, 235, 236, 237 Logical AND 100, 101, 102, 103, 104 Op Code Decoder 3 Logical Exclusive OR 368, 369, 370, 372, 373...
  • Page 408 ® eZ80 User Manual PEA IX+d 275 RES b, r 291 PEA IY+d 276 Reset Bit 288, 289, 291 Persistent Memory Mode Changes in ADL and Z80 Reset MIXED MEMORY Mode Flag 325 Modes 25 Restart 326 persistent mode 18...
  • Page 409 ® eZ80 User Manual RSMIX 325 SRA (HL) 348 RSMIX instruction 34 SRA (IX/Y+d) 349 RST instruction 34, 48 SRA r 350 RST n 326 SRL (HL) 352 SRL (IX/Y+d) 353 SRL r 354 Stack Pointer 48 Safeguards ix Stack Pointer Long register 10, 54, 219, 234, 235,...
  • Page 410 ® eZ80 User Manual Z80 memory page 10 Z80 Mode 11 XOR A, (HL) 368 Z80 mode vi, 2, 6, 7, 9, 10, 12, 18, 20, 21, 25, 26, XOR A, (IX/Y+d) 370 27, 28, 29, 30, 31, 32, 33, 34, 35, 37, 39, 40, 46,...

  • Page 411: Customer Support

    For answers to technical questions about the product, documentation, or any other issues with Zilog's offerings, please visit Zilog's Knowledge Base at: http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit Zilog's Technical Support at: http://support.zilog.com UM007714-0908...

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