ZiLOG Z8018 Series User Manual page 191

Z8018x
Family MPU User Manual
177
Flag Registers (F, F')
The flag registers store status bits (described in the next section) resulting
from executed instructions.
General Purpose Registers (BC, BC', DE, DE', HL, HL')
The General Purpose Registers are used for both address and data
operation. Depending on the instruction, each half (8 bits) of these
registers (B, C, D, E, H, and I) may also be used.
Interrupt Vector Register (I)
For interrupts that require a vector table address to be calculated (INT0
Mode 2, INT1, INT2, and internal interrupts), the Interrupt Vector
Register (I) provides the most significant byte of the vector table address.
I is cleared to during reset.
00H
R Counter (R)
The least significant seven bits of the R counter (R) count the number of
instructions executed by the Z80180. R increments for each CPU Op Code
fetch cycle (each M1 cycle). R is cleared to during reset.
00H
Index Registers (IX, and IY)
The Index Registers are used for both address and data operations. For
addressing, the contents of a displacement specified in the instruction are
added to or subtracted from the Index Register to determine an effective
operand address.
UM005004-0918