Table of Contents
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Table 44.
Stock and Exchange
Operation
Name
Mnemonics
Op Code
PUSH
PUSH zz
11zz 0101
PUSH IX
11 011 101
11 100 101
PUSH
PUSH IY
11 111 101
11 100 101
POP
POP zz
11 zz0 001
POP IX
11 011 101
11 100 001
POP IY
11 111 101
11 100 001
Addressing
Immed Ext
Ind
Reg RegI Imp Rel
S
D
Family MPU User Manual
Bytes States
Operation
D
1
11
zzLr→(SP-2)
zzHr→(SP-1)
SP
-2→SP
R
S/D
2
14
IXLr→(SP-2)
IXHr→(SP-1)
SP
-2→SP
R
S/D
2
14
IYLr→(SP-2)
IYHr→(SP-1)
SP
-2→SP
R
S
1
9
(SP + 1)
(SP)M→zzLx
SP
+ 2→SP
R
S/D
2
12
(SP + 1)
→IXLr
(SP)
M
SP
+ 2→SP
R
S/D
2
12
(SP + 1)
(SP)
-IYLr
M
SP
+ 2→SP
R
Z8018x
Flags
7 6 4 2
1 0
S Z H P/V N C
• • • •
• •
M
M
R
• • • •
• •
M
M
R
• • • •
• •
M
M
R
→xxHr(4)
• • • •
• •
M
R
→IXHr
• • • •
• •
M
R
→IYHr
• • • •
• •
M
R
UM005004-0918
227
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Do you have a question about the Z8018 Series and is the answer not in the manual?
Questions and answers
are there a timing diagrams for PUSH and POP instructions?
The timing diagrams for the PUSH and POP instructions for the ZiLOG Z8018 Series are as follows:
POP Instruction (e.g., POP IX or POP IY):
- Machine Cycle 1 (MC1): Fetch POP opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Read from memory at SP (Stack Pointer); data goes to low byte (e.g., IXL or IYL).
- Machine Cycle 4 (MC4): Read from memory at SP+1; data goes to high byte (e.g., IXH or IYH).
PUSH Instruction (e.g., PUSH IX or PUSH IY):
- Machine Cycle 1 (MC1): Fetch PUSH opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Decrement SP by 1 and write high byte (e.g., IXH or IYH) to memory at SP.
- Machine Cycle 4 (MC4): Decrement SP by 1 and write low byte (e.g., IXL or IYL) to memory at SP.
Each machine cycle includes three T-states (T1, T2, T3), and memory control signals (such as MREQ, RD, WR) are active as needed during these cycles.
This answer is automatically generated