Table of Contents
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Status Signals
PIN OUTPUTS IN EACH OPERATING MODE
Table 55 describes pin outputs in each operating mode.
Table 55.
Pin Outputs in Each Operating Mode
Mode
CPU
Op Code Fetch
Operation
(1st Op Code)
Op Code Fetch
(except 1 st Op
Code)
MemRead
Memory Write
I/O Read
I/O Write
Internal
Operation
Refresh
Interrupt
NMI
Acknowledge
INT0
Cycle
(1st Machine
INT1, INT2 &
Cycle)
Internal
Interrupts
BUS RELEASE
HALT
SLEEP
M1 MREQ IORQ RD WR RFSH HALT BUSACK ST
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
0
1
1
0
0
1
0
0
1
0
1
1
1
1
1
1
Z
Z
Z
0
0
1
0
1
1
1
1
Family MPU User Manual
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Z
1
1
0
1
1
0
1
1
1
0
1
Z8018x
287
Address
Data
BUS
BUS
0
A
IN
1
A
IN
1
A
IN
1
A
OUT
1
A
IN
1
A
OUT
1
A
IN
*
A
IN
0
A
IN
0
A
IN
0
A
IN
*
Z
IN
0
A
IN
1
1
IN
UM005004-0918
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