Table of Contents
Advertisement
Z8018x
Family MPU User Manual
188
Table 29.
Z8S180 DC Characteristics (Continued)
Symbol Item
VOH1 Output High Voltage
All outputs
VOH2 Output High Voltage
Output High Phi
VOL1
Output Low Voltage
All outputs
VOL2
Output Low Voltage
Output Low Phi
IIL
Input Leakage Current
all inputs except XTAL,
ETAL
ITL
Three-State Leakage
Current
ICC
Power Dissipation*
(Normal Operation)
Power Dissipation*
(SYSTEM STOP
Mode)
Power Dissipation*
(IDLE Mode)
Power Dissipation*
(STANDBY Mode)
CP
Pin Capacitance
Notes: * VIN min = V
V
= 5.0V
CC
UM005004-0918
Condition
IOH = –200 μA
IOH = –20 μA
IOH = –200 μA
IOL = 2.2 mA
IOL = 2.2 mA
VIN = 0.5 ~ VCC –0.5 –
VIN = 0.5 ~ VCC –0.5 –
f = 10 MHz
f = 20 MHz
f = 33 MHz
f = 10 MHz
f = 20 MHz
f = 33 MHz
f = 20 MHz
f = 33 MHz
External Oscillator,
Internal Clock Stops
VIN = 0V,
f = 1MHz
TA = 25°C
–1.0V. VIL max = 0.8V (All output terminals are a no load.)
CC
Minimum Typical Maximum Unit
2.4
–
–
V
–1.2
–
–
CC
V
–0.6
CC
–
–
0.45
–
–
0.45
–
1.0
–
1.0
–
15
–
30
50
60
100
–
1.5
–
3
6
5
9
–
4
10
–
5
10
–
–
12
V
V
V
V
μA
μA
mA
mA
mA
μA
pF
Advertisement
Table of Contents
Need help?
Do you have a question about the Z8018 Series and is the answer not in the manual?
Questions and answers
are there a timing diagrams for PUSH and POP instructions?
The timing diagrams for the PUSH and POP instructions for the ZiLOG Z8018 Series are as follows:
POP Instruction (e.g., POP IX or POP IY):
- Machine Cycle 1 (MC1): Fetch POP opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Read from memory at SP (Stack Pointer); data goes to low byte (e.g., IXL or IYL).
- Machine Cycle 4 (MC4): Read from memory at SP+1; data goes to high byte (e.g., IXH or IYH).
PUSH Instruction (e.g., PUSH IX or PUSH IY):
- Machine Cycle 1 (MC1): Fetch PUSH opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Decrement SP by 1 and write high byte (e.g., IXH or IYH) to memory at SP.
- Machine Cycle 4 (MC4): Decrement SP by 1 and write low byte (e.g., IXL or IYL) to memory at SP.
Each machine cycle includes three T-states (T1, T2, T3), and memory control signals (such as MREQ, RD, WR) are active as needed during these cycles.
This answer is automatically generated