Architecture; Table 2. Multiplexed Pin Descriptions - ZiLOG Z8018 Series User Manual

Z8018x
Family MPU User Manual
12

ARCHITECTURE

UM005004-0918
Table 2. Multiplexed Pin Descriptions
Multiplexed
Pins Descriptions
During RESET, this pin is initialized as A18 pin. If either
TOC1 or TOC0 bit of the Timer Control Register (TCR) is set
A18/TOUT
to 1, TOUT function is selected. If TOC1 and TOC0 bits are
cleared to 0, A18 function is selected.
During RESET, this pin is initialized as CKA
DREQ0
CKA0/ If either DM1 or SM1 in DMA Mode Register (DMODE) is
set to 1,
During RESET, this pin is initialized as CKA1 pin. If
CKA1D bit in ASCI control register ch 1 (CNTLA1) is set to
TEND0
CKA1/
1,
CKA1 function is selected.
During RESET, this pin is initialized as RXS pin. If CTS1E bit
CTS1
RXS/ in ASCI status register ch 1 (STAT1) is set to 1,
is selected. If CTS1E bit is 0, RXS function is selected.
The Z8X180 combines a high performance CPU core with a variety of
system and I/O resources useful in a broad range of applications. The CPU
core consists of five functional blocks: clock generator, bus state controller
(including dynamic memory refresh), interrupt controller, memory
management unit (MMU), and the central processing unit (CPU). The
integrated I/O resources make up the remaining four functional blocks:
•
Direct Memory Access (DMA) Control (2 channels)
•
Asynchronous Serial Communications Interface (ASCI, 2 channels),
DREQ0
function is always selected.
TEND0
function is selected. If CKA1D bit is set to 0,
pin.
0
CTS1
function