Table of Contents
Advertisement
Z8018x
Family MPU User Manual
288
Table 55.
Pin Outputs in Each Operating Mode (Continued)
Mode
Memory Read
Internal
Memory Write
DMA
I/O Read
I/O Write
RESET
PIN STATUS
UM005004-0918
M1 MREQ IORQ RD WR RFSH HALT BUSACK ST
1
0
1
0
1
1
1
1
1
1
•
1 : High
•
0 : Low
•
A : Programmable
•
Z : High Impedance
•
IN : Input
•
OUT : Output
•
* : Invalid
Tables 56 describes the status of each ping during RESET and LOW
POWER OPERATION modes.
1
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
Address
BUS
*
1
0
*
1
0
*
1
0
*
1
0
1
1
1
Data
BUS
A
IN
A
OUT
A
IN
A
OUT
Z
IN
Advertisement
Table of Contents
Need help?
Do you have a question about the Z8018 Series and is the answer not in the manual?
Questions and answers
are there a timing diagrams for PUSH and POP instructions?
The timing diagrams for the PUSH and POP instructions for the ZiLOG Z8018 Series are as follows:
POP Instruction (e.g., POP IX or POP IY):
- Machine Cycle 1 (MC1): Fetch POP opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Read from memory at SP (Stack Pointer); data goes to low byte (e.g., IXL or IYL).
- Machine Cycle 4 (MC4): Read from memory at SP+1; data goes to high byte (e.g., IXH or IYH).
PUSH Instruction (e.g., PUSH IX or PUSH IY):
- Machine Cycle 1 (MC1): Fetch PUSH opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Decrement SP by 1 and write high byte (e.g., IXH or IYH) to memory at SP.
- Machine Cycle 4 (MC4): Decrement SP by 1 and write low byte (e.g., IXL or IYL) to memory at SP.
Each machine cycle includes three T-states (T1, T2, T3), and memory control signals (such as MREQ, RD, WR) are active as needed during these cycles.
This answer is automatically generated