Figure 20. Halt Timing Diagram - ZiLOG Z8018 Series User Manual

.
HALT Op Code
Fetch Cycle
T1
Phi
INT1, NMI
–
A0 A19
HALT Op Code address
HALT
M1
MREQ
RD
Figure 20. HALT Timing Diagram
SLEEP Mode
SLEEP mode is entered by execution of the 2-byte SLP instruction.
SLEEP mode contains the following characteristics:
•
The internal CPU clock stops, reducing power consumption
•
The internal crystal oscillator does not stop
•
Internal and external interrupt inputs can be received
•
DRAM refresh cycles stop
•
I/O operations using on-chip peripherals continue
•
The internal DMAC stop
•
BUSREQ can be received and acknowledged
•
Address outputs go High and all other control signal outputs become
inactive High
HALT mode
T3 T1 T2
HALT Op Code address + 1
Family MPU User Manual
Interrupt
acknowledge cycle
T3 T1
UM005004-0918
Z8018x
33
T2