Table 57. Internal I/O Registers - ZiLOG Z8018 Series User Manual

Z8018x
Family MPU User Manual
294
Register
ASCI Control Register B
Channel 0:
ASCI Control Register B
Channel 1:
UM005004-0918
Table 57. Internal I/O Registers (Continued)
Mnemonics Address
CNTLB0 0
CNTLB1 0
2
MPBT MP
bit
invalid
during RESET 0
R/W
R/W R/W
Multi Processor Bit Transmit
* CTS: Depending on the condition 0f CTS Pin.
PS: Cleared to 0.
3
MPBT MP
bit
during RESET
invalid 0
R/W R/W R/W
Multi Processor Bit Transmit
General
(divide ratio=10)
divide ratio
SS2 1 0
DR=0 (X 16)
0 0 0 φ ÷ 160
÷
0 0 1 320
÷
0 1 0 640
÷
1280
0 1 1
÷
2560
1 0 0
÷
5120
1 0 1
÷
1 1 0 10240
1 1 1
External clock (frequency < φ ÷ 40)
Remarks
CTS/
SS1
PEO SS2
DR
PS
1
0 0
*
R/W R/W R/W R/W R/W
Divide Ratio
Parity Even or Odd
Clear to send/Prescale
Multi Processor
CTS/
PEO DR SS2
PS
0 0 0 1
R/W R/W R/W R/W
Divide Ratio
Parity Even or Odd
Clear to Send/Prescale
Multi Processor
PS=0 PS=1
(divide ratio=30)
DR=1 (X 64) DR=0 (X 16)
φ ÷ 480
φ ÷ 640
÷
÷ 960
1280
÷
÷
2560 1920
÷
÷ 5120 3840
÷
÷ 10240 7680
÷
÷
15360
20480
÷
÷
40960 30720
SS0
1
1
R/W
Clock Source and
Speed Select
SS1 SS0
1 1
R/W R/W
Clock Source and
Speed Select
DR=1 (X 64)
φ ÷
1920
÷
3840
÷
7680
÷
15360
÷
30720
÷
61440
÷
122880