Figure 32. Trap Timing Diagram -2Nd Op Code Undefined - ZiLOG Z8018 Series User Manual

stacked PC-1. If UFO is
equal to the stacked PC-2.
Bus Release cycle, Refresh cycle, DMA cycle, and WAIT cycle cannot be
inserted just after TTP state which is inserted for TRAP interrupt
sequence. Figure depicts TRAP Timing - 2nd Op Code undefined and
Figure illustrates Trap Timing - 3rd Op Code undefined.
2nd Op Code
Fetch Cycle
T1 T2
Phi
–
A0 A19
–
D0 D7
Undefined
Op Code
MI
MREQ
RD
WR
Figure 32.
, the starting address of the invalid instruction is
1
T3 Ti Ti Ti Ti
PC
TRAP Timing Diagram -2nd Op Code Undefined
Family MPU User Manual
PC Stacking
Ti T1 T2 T3 T1 T2
SP-2
SP-1
PCH
Z8018x
Restart from 0000H
Op Code
Fetch Cycle
T3 T1 T2 T3
0000H
PCL
UM005004-0918
71