Table 15. Channel 1 Transfer Mode - ZiLOG Z8018 Series User Manual

Z8018x
Family MPU User Manual
102
DMA I/O Address Register Ch. 1 (IAR1B: 2DH) (Z8S180/L180-Class Processor Only)
Bit 7
Bit/Field
R/W R/W
Reset 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field
7
6
–
5 4 Reserved
3
UM005004-0918
Table 15. Channel 1 Transfer Mode
DIM1 DIM0 Transfer Mode
0 0 Memory
0 1 Memory
1 0 I/O
1 1 I/O
6 5
R/W
0
R/W Value Description
R/W
0
1
R/W
R/W 0
R/W 0
1
to
I/O
to
I/O
to
Memory
to
Memory
4 3
Reserved
R/W R/W
0 0
Alternating Channels
DMA Channels are independent
Toggle between DMA channels for same device
Currently selected DMA channel when Bit 7 = 1
Reserved. Must be 0.
TOUT/DREQ is DREQ In
TOUT/DREQ is TOUT Out
Address Increment/Decrement
MARI +1, IAR1 fixed
MARI -1, IAR1 fixed
IAR1 fixed, MAR1+1
IAR1 fixed, MAR1-1
2 1
R/W
0
0