Figure 4. Z80180/Z8S180/Z8L180 Block Diagram - ZiLOG Z8018 Series User Manual

Z8018x
Family MPU User Manual
6
Phi
A18/TOUT
TXS
RXS/CTS1
CKS
Figure 4.
UM005004-0918
Timing
Generator
16-bit
Programmable
Reload
Timers
Clocked
Serial I/O
Port
MMU
Address
Buffer
–
A0 A19
Z80180/Z8S180/Z8L180 Block Diagram
Bus State Control
CPU
DMACs
(2)
Asynchronous
(Channel 0)
Asynchronous
SCI
(channel 1)
Data
Buffer
–
D0 DF
Interrupt
DREQ1
TEND1
TXA0
CKA0/DREQ0
RXA0
SCI
RTS0
CTS0
DCD0
TXA1
CKA1/TEND0
RXA1
V
CC
V
SS