ZiLOG Z8018 Series User Manual page 105

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DREQ Input
Level- and edge-sense DREQ input detection are selectable.
TEND Output Used to indicate DMA completion to external devices.
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Transfer Rate
Each byte transfer occurs every 6 clock cycles. Wait States can be
inserted in DMA cycles for slow memory or I/O devices. At the
system clock (φ) = 6 MHz, the DMA transfer rate is as high as 1.0
megabytes/second (no Wait States).
There is an additional feature disc for DMA interrupt request by DMA
END. Each channel has the following additional specific capabilities:
Channel 0
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Memory to memory
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Memory to I/O
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Memory to memory mapped I/O transfers.
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Memory address increment, decrement, no-change
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Burst or cycle steal memory to/from memory transfers
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DMA to/from both ASCI channels
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Higher priority than DMAC channel 1
Channel 1
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Memory to/from I/O transfer
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Memory address increment, decrement
DMAC Registers
Each channel of the DMAC (channel 0, 1) contains three registers
specifically associated with that channel.
Family MPU User Manual
UM005004-0918
Z8018x
91