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Z8018x
Family MPU User Manual
116
UM005004-0918
The key functions for ASCI on Z80180, Z8S180 and Z8L180 class
processors are listed below. Each channel is independently
programmable.
•
Full-duplex communication
•
7- or 8-bit data length
•
Program controlled 9th data bit for multiprocessor communication
•
1 or 2 stop bits
•
Odd, even, no parity
•
Parity, overrun, framing error detection
•
Programmable baud rate generator, /16 and /64 modes
•
Modem control signals – Channel 0 contains DCD0, CTS0 and RTS0;
Channel 1 contains CTS1
•
Programmable interrupt condition enable and disable
•
Operation with on-chip DMAC
ASCI Block Diagram for the Z8S180/Z8L180-Class
Processors
Figure 52 illustrates the ASCI block diagram.
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Questions and answers
are there a timing diagrams for PUSH and POP instructions?
The timing diagrams for the PUSH and POP instructions for the ZiLOG Z8018 Series are as follows:
POP Instruction (e.g., POP IX or POP IY):
- Machine Cycle 1 (MC1): Fetch POP opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Read from memory at SP (Stack Pointer); data goes to low byte (e.g., IXL or IYL).
- Machine Cycle 4 (MC4): Read from memory at SP+1; data goes to high byte (e.g., IXH or IYH).
PUSH Instruction (e.g., PUSH IX or PUSH IY):
- Machine Cycle 1 (MC1): Fetch PUSH opcode.
- Machine Cycle 2 (MC2): Fetch address code.
- Machine Cycle 3 (MC3): Decrement SP by 1 and write high byte (e.g., IXH or IYH) to memory at SP.
- Machine Cycle 4 (MC4): Decrement SP by 1 and write low byte (e.g., IXL or IYL) to memory at SP.
Each machine cycle includes three T-states (T1, T2, T3), and memory control signals (such as MREQ, RD, WR) are active as needed during these cycles.
This answer is automatically generated