Figure 40. Int0 Interrupt Mode 2 Timing Diagram - ZiLOG Z8018 Series User Manual

Z8018x
Family MPU User Manual
80
Last MC
Phi
INT0
–
A0 A19
M1
MREQ
IORQ
RD
WR
–
D0 D7
ST
UM005004-0918
Vector Lower
Address Read
T1
T3
T2 Ti
TW*
TW*
PC
Lower Vector
Figure 40. INT0 Interrupt Mode 2 Timing Diagram
INT1, INT2
The operation of external interrupts INT1 and INT2 is a vector mode
similar to INT0 Mode 2. The difference is that INT1 and INT2 generate
the low-order byte of vector table address using the IL (Interrupt Vector
Low) register rather than fetching it from the data bus. This difference is
INT0 Acknowledge Cycle
PC is pushed onto stack
T2 T3
T1 T1 T2 T3
SP-1
SP-2
Starting Address
(Lower Address)
PCL
PCH
*Two Wait States are automatically inserted
Interrupt
Manipulation
Cycle
T1
T1 T2 T3 T2
Starting address
Vector Vector+1
Starting Address
(Upper Address)
Op Code
Fetch Cycle
T2
T1 T3