ZiLOG Z8018 Series User Manual page 291

Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction Cycle
MC1
MC2
SET b, (IX+d)
MC3
SET b, (IY+d)
RES b, (IX+d)
MC4
RES b, (IY+d)
MC5
MC6
MC7
MC1
SLP**
MC2
—
MC1
MC2
TSTIO m**
MC3
MC4
States Address Data
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
T1T2T3 1st operand d
Address
T1T2T3 3rd Op Code 3rd Op
Address Code
T1T2T3 IX+d DATA
IY+d
Ti * Z
T1T2T3 IX+ d DATA
IY+d
T1T2T3 1st Op Code 1stOp
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
— 7FFFFH Z
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
T1T2T3 1st operand m
Address
T1T2T3 C to A0~A7 DATA
00H to
A8~A15
Family MPU User Manual
RD WR MREQ IORQ M1 HALT ST
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
1 1 1 1
1 0 0 1
0 1 0 1
0 1 0 1
1 1 1 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 1 0
Z8018x
277
0 1 0
0 1 1
1 1 1
0 1 1
1 1 1
1 1 1
1 1 1
0 1 0
0 1 1
1 0 1
0 1 0
0 1 1
1 1 1
1 1 1
UM005004-0918