ZiLOG Z8018 Series Manuals

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ZiLOG Z8018 Series User Manual (317 pages)

MPU

Brand: ZiLOG | Category: Computer Hardware | Size: 2 MB

Table of Contents
5
Z80180, Z8S180, Z8L180 MPU Operation
15
Features
15
General Description
15
Figure 1. 64-Pin DIP
17
Figure 2. 68-Pin PLCC
18
Figure 3. 80-Pin QFP
19
Figure 4. Z80180/Z8S180/Z8L180 Block Diagram
20
Pin Description
21
Table 1. Status Summary
24
Architecture
26
Table 2. Multiplexed Pin Descriptions
26
Operation Modes
29
Figure 5. Operation Mode Control Register
29
Figure 6. M1 Temporary Enable Timing
30
Figure 7. I/O Read and Write Cycles with IOC
31
Figure 8. I/O Read and Write Cycles with IOC
31
CPU Timing
32
Figure 9. Op Code Fetch (Without Wait State) Timing Diagram
33
Figure 10. Op Code Fetch (with Wait State) Timing Diagram
34
Figure 13. I/O Read/Write Timing Diagram
37
Figure 14. Instruction Timing Diagram
38
Figure 15. RESET Timing Diagram
39
Figure 16. Bus Exchange Timing During Memory Read
40
Wait State Generator
41
Figure 17. Bus Exchange Timing During CPU Internal Operation
41
Figure 18. WAIT Timing Diagram
42
Figure 19. Memory and I/O Wait State Insertion (DCNTL - Dma/Wait Control Register)
43
Table 3. Memory Wait States
43
Table 4. Wait State Insertion
44
HALT and Low Power Operation Modes (Z80180-Class Processors Only)
45
Figure 20. HALT Timing Diagram
47
Figure 21. SLEEP Timing Diagram
49
Low Power Modes (Z8S180/Z8L180 Only)
50
Add-On Features
50
STANDBY Mode
51
Table 5. Power-Down Modes (Z8S180/Z8L180-Class Processor Only)
51
STANDBY Mode Exit Wiht BUS REQUEST
52
STANDBY Mode Exit with External Interrupts
53
IDLE Mode
54
STANDBY-QUICK RECOVERY Mode
55
Internal I/O Registers
55
Figure 22. I/O Address Relocation
57
Table 6. I/O Address Map for Z80180-Class Processors Only
58
Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only)
62
Figure 23. Logical Address Mapping Examples
69
Figure 24. Physical Address Transition
70
Figure 25. MMU Block Diagram
70
Figure 26. I/O Address Translation
71
Figure 27. Logical Memory Organization
72
Figure 28. Logical Space Configuration
73
MMU Register Description
74
Figure 29. Physical Address Generation
78
Figure 30. Physical Address Generation 2
78
Interrupts
79
Figure 31. Interrupt Sources
79
Table 8. State of IEF1 and IEF2
83
Figure 32. TRAP Timing Diagram -2Nd Op Code Undefined
85
Figure 33. TRAP Timing - 3Rd Op Code Undefined
86
Figure 34. NMI Use
88
Figure 35. NMI Timing
89
Figure 36. INT0 Mode 0 Timing Diagram
90
Figure 37. INT0 Mode 1 Interrupt Sequence
91
Figure 38. INT0 Mode 1 Timing
92
Figure 39. INT0 Mode 2 Vector Acquisition
93
Figure 40. INT0 Interrupt Mode 2 Timing Diagram
94
Figure 41. INT1, INT2 Vector Acquisition
95
Interrupt Acknowledge Cycle Timings
96
Table 9. Vector Table
96
Interrupt Sources During RESET
97
Figure 42. RETI Instruction Sequence
98
Table 10. RETI Control Signal States
99
Dynamic RAM Refresh Control
100
Figure 43. INT1, INT2 and Internal Interrupts Timing Diagram
100
Figure 44. Refresh Cycle Timing Diagram
101
Table 11. DRAM Refresh Intervals
103
DMA Controller (DMAC)
104
Figure 45. DMAC Block Diagram
107
Table 12. Channel 0 Destination
112
Table 13. Channel 0 Source
113
Table 14. Transfer Mode Combinations
114
Table 15. Channel 1 Transfer Mode
116
Figure 46. DMA Timing Diagram-CYCLE STEAL Mode
120
Figure 47. CPU Operation and DMA Operation DREQ0 Is Programmed for Level-Sense
121
Figure 48. CPU Operation and DMA Operation DREQ0 Is Programmed for Edge-Sense
122
Figure 49. TEND0 Output Timing Diagram
122
Table 16. DMA Transfer Request
124
Figure 50. DMA Interrupt Request Generation
128
Asynchronous Serial Communication Interface (ASCI)
129
Figure 51. NMI and DMA Operation Timing Diagram
129
Figure 52. ASCI Block Diagram
131
Table 17. Data Formats
145
Table 18. Divide Ratio
148
Figure 53. DCD0 Timing Diagram
153
Figure 54. RTS0 Timing Diagram
154
Figure 55. ASCI Interrupt Request Circuit Diagram
154
Figure 56. ASCI Clock
155
Table 19. ASCI Baud Rate Selection
156
Baud Rate Generator
157
(Z8S180/Z8L180-Class Processors Only)
157
Table 20. Clock Mode Bit Values
158
Table 21. 2^Ss Values
159
Clocked Serial I/O Port (CSI/O)
160
CSI/O Registers Description
161
Figure 57. CSI/O Block Diagram
161
Table 22. CSI/O Baud Rate Selection
164
Figure 58. CSI/O Interrupt Request Generation
165
Figure 59. Transmit Timing Diagram-Internal Clock
167
Figure 60. Transmit Timing-External Clock
168
Figure 61. CSI/O Receive Timing-Internal Clock
169
Programmable Reload Timer (PRT)
170
Figure 62. CSI/O Receive Timing-External Clock
170
Figure 63. PRT Block Diagram
171
Table 23. Timer Output Control
177
Figure 65. Timer Output Timing Diagram
178
Figure 66. PRT Interrupt Request Generation
178
Table 24. E Clock Timing in each Condition
180
Figure 67. E Clock Timing Diagram
181
Figure 68. E Clock Timing in BUS RELEASE Mode
181
Figure 69. E Clock Timing in SLEEP Mode and
182
Figure 70. External Clock Interface
183
Table 25. Z8X180 Operating Frequencies
183
Figure 71. Clock Generator Circuit
184
Figure 72. Circuit Board Design Rules
184
Figure 73. Example of Board Design
185
Miscellaneous
186
Software Architecture
187
Instruction Set
187
Table 26. Instruction Set Summary
187
CPU Registers
189
Figure 74. CPU Register Configurations
190
Figure 75. Register Direct - Bit Field Definitions
195
Figure 76. Register Indirect Addressing
195
Figure 77. Indexed Addressing
196
Figure 78. Extended Addressing
196
Figure 79. Immediate Addressing
197
Figure 80. Relative Addressing
197
DC Characteristics
199
Absolute Maximum Rating
199
Table 27. Absolute Maximum Rating
199
Z80180 DC Characteristics
200
Table 28. Z80180 DC Characteristics
200
Z8S180 DC Characteristics
201
Table 29. Z8S180 DC Characteristics
201
Z8L180 DC Characteristics
203
Table 30. Z8L180 DC Characteristics
203
AC Characteristics
207
AC Characteristics-Z8S180
207
Table 31. Z8S180 AC Characteristics
208
Timing Diagrams
211
Figure 81. AC Timing Diagram 1
211
Figure 82. AC Timing Diagram 2
212
Figure 84. DMA Control Signals
214
Figure 85. E Clock Timing (Memory R/W Cycle) (I/O R/W Cycle)
215
Figure 87. E Clock Timing
216
Figure 88. Timer Output Timing
216
Figure 89. SLP Execution Cycle Timing Diagram
217
Figure 90. CSI/O Receive/Transmit Timing Diagram
218
Figure 91. External Clock Rise Time and Fall Time
218
Figure 92. Input Rise Time and Fall Time
218
Standard Test Conditions
219
Figure 93. Test Setup
219
Instruction Set
221
Register
221
Bit
221
Table 32. Register Values
221
Condition
222
Table 33. Bit Values
222
Table 34. Instruction Values
222
Restart Address
223
Flag
223
Table 35. Address Values
223
Table 36. Flag Conditions
223
Miscellaneous
224
Table 37. Operations Mnemonics
224
Data Manipulation Instructions
225
Table 38. Arithmetic and Logical Instructions (8-Bit)
225
Table 39. Rotate and Shift Instructions
231
Table 40. Arithmetic Instructions (16-Bit)
235
Data Transfer Instructions
236
Table 41. 8-Bit Load
236
Table 42. 16-Bit Load
238
Table 43. Block Transfer
239
Table 44. Stock and Exchange
241
Program and Control Instructions
243
Table 45. Program Control Instructions
243
Table 46. I/O Instructions
245
Special Control Instructions
249
Table 47. Special Control Instructions
249
Instruction Summary
251
Op Code Map
261
Table 48. 1St Op Code Map Instruction Format: XX
261
Table 49. 2Nd Op Code Map Instruction Format: CB XX
263
Table 50. 2Nd Op Code Map Instruction Format: ED XX
264
Bus Control Signal Conditions
265
Bus and Control Signal Condition in each Machine Cycle
265
Table 51. Bus and Control Signal Condition in each Machine Cycle
265
Interrupts
293
Table 52. Interrupts
294
Operating Modes Summary
295
Request Acceptances in each Operating Mode
295
Request Priority
296
Table 53. Request Acceptances in each Operating Mode
296
Table 54. the Z80180 Types of Requests
296
Operation Mode Transition
297
Other Operation Mode Transitions
299
Status Signals
301
Pin Outputs in each Operating Mode
301
Table 55. Pin Outputs in each Operating Mode
301
Pin Status
302
Table 56. Pin Status During RESET and LOW POWER OPERATION Modes
303
I/O Registers
307
Internal I/O Registers
307
Table 57. Internal I/O Registers
308
Ordering Information
317

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