ZiLOG Z8018 Series User Manual page 266

Z8018x
Family MPU User Manual
252
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction Cycle
ADD A,g MC1
ADC A,g
SUB g
MC2
SBC A,g
AND g
OR g
XOR g
CP g
ADD A,m MC1
ADC A,m
SUB m
MC2
SBC A,m
AND m
OR m
XOR m
CP m
ADD A, (HL) MC1
ADC A, (HL)
SUB (HL)
MC2
SBC A, (HL)
AND HU
OR (HL)
XOR (HL)
CP (HL)
ADD A, (IX+ d) MC1
ADD A, (IY+d)
ADC A, (IX+d)
MC2
ADC A, (IY+d)
SUB (lX+d)
SUB (IY+d)
SBC A, (IX+ d)
SBC A, (IY+ d) MC3
AND (IX+d)
UM005004-0918
States Address Data
T1T2T3 1st Op Code 1st Op
Address Code
Ti * Z
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 1st operand m
Address
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 HL DATA
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
T1T2T3 1st operand d
Address
RD WR MREQ IORQ M1 HALT ST
0 1 0 1
1 1 1 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0
1 1 1
0 1 0
1 1 1
0 1 0
1 1 1
0 1 0
0 1 1
1 1 1