ZiLOG Z8018 Series User Manual page 312

Z8018x
Family MPU User Manual
298
Register
Timer Data Register
Channel 1L:
Timer Data Register
Channel 1H:
Timer Reload Register
Channel 1L
Timer Reload Register
Channel 1H:
Free Running Counter:
DMA Source Address
Register Channel 0L:
DMA Source Address
Register Channel 0H:
DMA Source Address
Register Channel 0B:
DMA Destination Address
Register Channel 0L:
DMA Destination Address
Register Channel 0H:
DMA Destination Address
Register Channel 0B:
DMA Byte Count Register
Channel 0L:
DMA Byte Count Register
Channel 0H:
DMA Memory Address
Register
Channel 1L:
DMA Memory Address
Register
Channel 1H:
UM005004-0918
Table 57. Internal I/O Registers (Continued)
Mnemonics Address
TMDR1L 1
TMDR1H 1
RLDR1L 1
RLDR1H 1
FRC 1
SAR0L 2
SAR0H 2
SAR0B 2
DAR0L 2
DAR0H 2
DAR0B 2
BCROL 2
BCROH 2
MAR1L 2
MAR1H 2
4
5
6
7
8
Read only
0
1
2
Bits 0-2 (3) are used for SAR0B
A *, A , A ,
19 18 17
X X 0
3
X X 0
X X 1
X X 1
4
5
Bits 0-2 (3) are used for DAR0B
A *, A , A ,
19 18 17
X X 0
6
X X 0
X X 1
X X 1
7
8
9
* In the R1 and Z mask, these DMAC registers are expanded from 4 bits to 3 bits in the
package version of CP-68.
Remarks
DMA Transfer Request
A
16
0
DREQ (external)
0
1
RDR0 (ASCI0)
0
RDR1 (ASCI1)
1
Not used
DMA Transfer Request
A
16
0
(external)
DREQ
0
1
TDR0 (ASCI0)
0
TDR1 (ASCI1)
1
Not used