Table 6. I/O Address Map For Z80180-Class Processors Only - ZiLOG Z8018 Series User Manual

Z8018x
Family MPU User Manual
44
Table 6. I/O Address Map for Z80180-Class Processors Only
Register
ASCI ASCI Control Register A Ch 0
ASCI Control Register A Ch 1
ASCI Control Register B Ch 0
ASCI Control Register B Ch 1
ASCI Status Register Ch 0
ASCI Status Register Ch 1
ASCI Transmit Data Register Ch 0
ASCI Transmit Data Register Ch 1
ASCI Receive Data Register Ch 0
ASCI Receive Data Register Ch 1
CSI/O CSI/O Control Register
CSI/O Transmit/Receive Data Register TRD
UM005004-0918
address to . These instructions are IN0, OUT0, OTIM, OTIMR, OTDM,
0
OTDMR and TSTIO (see Instruction Set).
When writing to an internal I/O register, the same I/O write occurs on the
external bus. However, the duplicate external I/O write cycle exhibits
internal I/O write cycle timing. For example, the WAIT input and
programmable Wait State generator are ignored. Similarly, internal I/O
read cycles also cause a duplicate external I/O read cycle. However, the
external read data is ignored by the Z8X180.
Normally, external I/O addresses should be chosen to avoid overlap with
internal I/O addresses and duplicate I/O accesses.
Mnemonic Binary
CNTLA0 XX000000
CNTLA1 XX000001
CNTLB0 XX000010
CNTLB1 XX000011
STAT0 XX000100
STAT1 XX000101
TDR0 XX000110
TDR1 XX000111
RDR0 XX001000
RDR1 XX001001
CNTR XX001010
XX1011
Address
Hex Page
00H 125
01H 128
02H 132
03H 132
04H 120
05H 123
06H 118
07H 118
08H 119
09H 119
0AH 147
0BH 149